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| author | Colin LeMahieu <colinl@codeaurora.org> | 2014-11-18 20:28:11 +0000 |
|---|---|---|
| committer | Colin LeMahieu <colinl@codeaurora.org> | 2014-11-18 20:28:11 +0000 |
| commit | efa74e0280b28916b101d4e332b90b472d73172e (patch) | |
| tree | ed6b5aed90af8b0f0d71c31f169307192d46bd6d /llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp | |
| parent | e53e8c8e5888debe378c0cf35fcd4efb03c4af03 (diff) | |
| download | bcm5719-llvm-efa74e0280b28916b101d4e332b90b472d73172e.tar.gz bcm5719-llvm-efa74e0280b28916b101d4e332b90b472d73172e.zip | |
[Hexagon] Converting from ADD_rr to A2_add which has encoding bits.
Adding test to show correct instruction selection and encoding.
llvm-svn: 222249
Diffstat (limited to 'llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp index 1fc4f7f4979..0b32d8cd6e0 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -1295,10 +1295,12 @@ bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const { switch (MI->getOpcode()) { default: return false; + case Hexagon::A2_paddf: + case Hexagon::A2_paddfnew: + case Hexagon::A2_paddt: + case Hexagon::A2_paddtnew: case Hexagon::ADD_ri_cPt: case Hexagon::ADD_ri_cNotPt: - case Hexagon::ADD_rr_cPt: - case Hexagon::ADD_rr_cNotPt: case Hexagon::XOR_rr_cPt: case Hexagon::XOR_rr_cNotPt: case Hexagon::AND_rr_cPt: |
