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authorColin LeMahieu <colinl@codeaurora.org>2014-11-21 21:54:59 +0000
committerColin LeMahieu <colinl@codeaurora.org>2014-11-21 21:54:59 +0000
commit310991c66f902d5b579c9226e55b5d4ee70caa53 (patch)
tree7dc0f430f9a06cbd7372b94cf30acb9b75bdfe64 /llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
parente9a09c74fa925e8aed2de0f12cce8d86215955d3 (diff)
downloadbcm5719-llvm-310991c66f902d5b579c9226e55b5d4ee70caa53.tar.gz
bcm5719-llvm-310991c66f902d5b579c9226e55b5d4ee70caa53.zip
[Hexagon] Adding sxth instruction.
llvm-svn: 222577
Diffstat (limited to 'llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp')
-rw-r--r--llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp8
1 files changed, 5 insertions, 3 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
index 3c7d63487cb..29502eea267 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -716,7 +716,7 @@ bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
case Hexagon::ASLH:
case Hexagon::ASRH:
case Hexagon::A2_sxtb:
- case Hexagon::SXTH:
+ case Hexagon::A2_sxth:
case Hexagon::ZXTB:
case Hexagon::ZXTH:
return Subtarget.hasV4TOps();
@@ -1315,6 +1315,10 @@ bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
case Hexagon::A2_pxorfnew:
case Hexagon::A2_pxort:
case Hexagon::A2_pxortnew:
+ case Hexagon::A4_psxthf:
+ case Hexagon::A4_psxthfnew:
+ case Hexagon::A4_psxtht:
+ case Hexagon::A4_psxthtnew:
case Hexagon::A4_psxtbf:
case Hexagon::A4_psxtbfnew:
case Hexagon::A4_psxtbt:
@@ -1328,8 +1332,6 @@ bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
case Hexagon::ASLH_cNotPt_V4:
case Hexagon::ASRH_cPt_V4:
case Hexagon::ASRH_cNotPt_V4:
- case Hexagon::SXTH_cPt_V4:
- case Hexagon::SXTH_cNotPt_V4:
case Hexagon::ZXTB_cPt_V4:
case Hexagon::ZXTB_cNotPt_V4:
case Hexagon::ZXTH_cPt_V4:
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