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authorBenjamin Kramer <benny.kra@googlemail.com>2015-08-08 18:27:36 +0000
committerBenjamin Kramer <benny.kra@googlemail.com>2015-08-08 18:27:36 +0000
commitdf005cbe198160b541d473ebe18aee3572d1cf16 (patch)
treee158a70cfc8b09d08c8911ab5378e5b50929c011 /llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
parent9bb8ef03a2bf081e26400a3b21e9ff476a22c88f (diff)
downloadbcm5719-llvm-df005cbe198160b541d473ebe18aee3572d1cf16.tar.gz
bcm5719-llvm-df005cbe198160b541d473ebe18aee3572d1cf16.zip
Fix some comment typos.
llvm-svn: 244402
Diffstat (limited to 'llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp')
-rw-r--r--llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp b/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
index 6905c4f6d12..d9675b5173d 100644
--- a/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
@@ -250,7 +250,7 @@ Register HexagonGenPredicate::getPredRegFor(const Register &Reg) {
unsigned NewPR = MRI->createVirtualRegister(PredRC);
// For convertible instructions, do not modify them, so that they can
- // be coverted later. Generate a copy from Reg to NewPR.
+ // be converted later. Generate a copy from Reg to NewPR.
if (isConvertibleToPredForm(DefI)) {
MachineBasicBlock::iterator DefIt = DefI;
BuildMI(B, std::next(DefIt), DL, TII->get(TargetOpcode::COPY), NewPR)
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