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| author | Craig Topper <craig.topper@gmail.com> | 2015-12-05 07:13:35 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2015-12-05 07:13:35 +0000 |
| commit | e5e035a3a86a8491b4e05395b73ec257438dc4af (patch) | |
| tree | f2e2be1ac726e2830bcde551a8ff0bd160e108b5 /llvm/lib/Target/Hexagon/HexagonGenMux.cpp | |
| parent | 58ee28410a29d9cd084c03d2dfb22aba53ef4029 (diff) | |
| download | bcm5719-llvm-e5e035a3a86a8491b4e05395b73ec257438dc4af.tar.gz bcm5719-llvm-e5e035a3a86a8491b4e05395b73ec257438dc4af.zip | |
Replace uint16_t with the MCPhysReg typedef in many places. A lot of physical register arrays already use this typedef.
llvm-svn: 254843
Diffstat (limited to 'llvm/lib/Target/Hexagon/HexagonGenMux.cpp')
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonGenMux.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonGenMux.cpp b/llvm/lib/Target/Hexagon/HexagonGenMux.cpp index b4ebd9140e7..c059d566709 100644 --- a/llvm/lib/Target/Hexagon/HexagonGenMux.cpp +++ b/llvm/lib/Target/Hexagon/HexagonGenMux.cpp @@ -120,10 +120,10 @@ void HexagonGenMux::getDefsUses(const MachineInstr *MI, BitVector &Defs, // First, get the implicit defs and uses for this instruction. unsigned Opc = MI->getOpcode(); const MCInstrDesc &D = HII->get(Opc); - if (const uint16_t *R = D.ImplicitDefs) + if (const MCPhysReg *R = D.ImplicitDefs) while (*R) expandReg(*R++, Defs); - if (const uint16_t *R = D.ImplicitUses) + if (const MCPhysReg *R = D.ImplicitUses) while (*R) expandReg(*R++, Uses); |

