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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-06-24 15:50:29 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-06-24 15:50:29 +0000 |
| commit | e3a676e9adba668a7da944766218e98dd4b2c10a (patch) | |
| tree | 632a983ae9fe72b635cf72262bf2e9a0cbe6dce3 /llvm/lib/Target/Hexagon/HexagonGenMux.cpp | |
| parent | 3260ef16bbdecc391d7da8fe3bbe19585f6ccb19 (diff) | |
| download | bcm5719-llvm-e3a676e9adba668a7da944766218e98dd4b2c10a.tar.gz bcm5719-llvm-e3a676e9adba668a7da944766218e98dd4b2c10a.zip | |
CodeGen: Introduce a class for registers
Avoids using a plain unsigned for registers throughoug codegen.
Doesn't attempt to change every register use, just something a little
more than the set needed to build after changing the return type of
MachineOperand::getReg().
llvm-svn: 364191
Diffstat (limited to 'llvm/lib/Target/Hexagon/HexagonGenMux.cpp')
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonGenMux.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonGenMux.cpp b/llvm/lib/Target/Hexagon/HexagonGenMux.cpp index acff2476164..cdafbc20ab8 100644 --- a/llvm/lib/Target/Hexagon/HexagonGenMux.cpp +++ b/llvm/lib/Target/Hexagon/HexagonGenMux.cpp @@ -303,8 +303,8 @@ bool HexagonGenMux::genMuxInBlock(MachineBasicBlock &B) { std::advance(It2, MaxX); MachineInstr &Def1 = *It1, &Def2 = *It2; MachineOperand *Src1 = &Def1.getOperand(2), *Src2 = &Def2.getOperand(2); - unsigned SR1 = Src1->isReg() ? Src1->getReg() : 0; - unsigned SR2 = Src2->isReg() ? Src2->getReg() : 0; + Register SR1 = Src1->isReg() ? Src1->getReg() : Register(); + Register SR2 = Src2->isReg() ? Src2->getReg() : Register(); bool Failure = false, CanUp = true, CanDown = true; for (unsigned X = MinX+1; X < MaxX; X++) { const DefUseInfo &DU = DUM.lookup(X); |

