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| author | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2018-03-28 19:38:29 +0000 |
|---|---|---|
| committer | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2018-03-28 19:38:29 +0000 |
| commit | 440ba3ae5cbdefea5f4a03c39f149b9db96ccd55 (patch) | |
| tree | 2aca1ce5c6dfaae1b9722666ea0b0393f0d4b61e /llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp | |
| parent | eed882022f6e997942d3e4f0bc07d4dadc3cbd57 (diff) | |
| download | bcm5719-llvm-440ba3ae5cbdefea5f4a03c39f149b9db96ccd55.tar.gz bcm5719-llvm-440ba3ae5cbdefea5f4a03c39f149b9db96ccd55.zip | |
[Hexagon] Add support for "new" circular buffer intrinsics
These instructions have been around for a long time, but we
haven't supported intrinsics for them. The "new" versions use
the CSx register for the start of the buffer instead of the K
field in the Mx register.
We need to use pseudo instructions for these instructions until
after register allocation. The problem is that these instructions
allocate a M0/CS0 or M1/CS1 pair. But, we can't generate code for
the CSx set-up until after register allocation when the Mx
register has been fixed for the instruction.
There is a related clang patch.
Patch by Brendon Cahoon.
llvm-svn: 328724
Diffstat (limited to 'llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp index e8c43de8529..f2f4598ba09 100644 --- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp @@ -1867,11 +1867,11 @@ bool HexagonFrameLowering::expandSpillMacros(MachineFunction &MF, Changed |= expandCopy(B, I, MRI, HII, NewRegs); break; case Hexagon::STriw_pred: - case Hexagon::STriw_mod: + case Hexagon::STriw_ctr: Changed |= expandStoreInt(B, I, MRI, HII, NewRegs); break; case Hexagon::LDriw_pred: - case Hexagon::LDriw_mod: + case Hexagon::LDriw_ctr: Changed |= expandLoadInt(B, I, MRI, HII, NewRegs); break; case Hexagon::PS_vstorerq_ai: |
