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authorKrzysztof Parzyszek <kparzysz@codeaurora.org>2018-07-10 12:57:49 +0000
committerKrzysztof Parzyszek <kparzysz@codeaurora.org>2018-07-10 12:57:49 +0000
commitc052451a02c30b5335a72d29e7dc16aef98f7e23 (patch)
treeeb195f1eba04ff060f7e75bae49c5874715bc160 /llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
parent6a9c719ee1be4562a9e16f2c71ac3e51ef9c4292 (diff)
downloadbcm5719-llvm-c052451a02c30b5335a72d29e7dc16aef98f7e23.tar.gz
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[Hexagon] Add implicit uses even when untied explicit uses are present
An explicit untied use is not sufficient to maintain liveness of a register redefined in a predicated instruction. For example %1 = COPY %0 ... %1 = A2_paddif %2, %1, 1 could become $r1 = COPY $r0 ... $r1 = A2_paddif $p0, $r1, 1 and later $r1 = COPY $r0 ;; this is not really dead! ... $r1 = A2_paddif $p0, $r0, 1 llvm-svn: 336662
Diffstat (limited to 'llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp')
-rw-r--r--llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp8
1 files changed, 6 insertions, 2 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
index d3222a63ead..7e774674e0c 100644
--- a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
@@ -499,14 +499,18 @@ void HexagonExpandCondsets::updateDeadsInRange(unsigned Reg, LaneBitmask LM,
if (!Op.isReg() || !DefRegs.count(Op))
continue;
if (Op.isDef()) {
- ImpUses.insert({Op, i});
+ // Tied defs will always have corresponding uses, so no extra
+ // implicit uses are needed.
+ if (!Op.isTied())
+ ImpUses.insert({Op, i});
} else {
// This function can be called for the same register with different
// lane masks. If the def in this instruction was for the whole
// register, we can get here more than once. Avoid adding multiple
// implicit uses (or adding an implicit use when an explicit one is
// present).
- ImpUses.erase(Op);
+ if (Op.isTied())
+ ImpUses.erase(Op);
}
}
if (ImpUses.empty())
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