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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-12-23 14:39:01 -0500 |
|---|---|---|
| committer | Matt Arsenault <arsenm2@gmail.com> | 2020-01-04 12:36:05 -0500 |
| commit | 5eed4e2664aa7187f46eb12e45a376d7ab7dd308 (patch) | |
| tree | cf437c0668e36473f30b2bcbb490bb16b3e1fcea /llvm/lib/Target/Hexagon/HexagonDepTimingClasses.h | |
| parent | 4c6c4e2fce285c16b66a147afb287f7d4fc3c2e1 (diff) | |
| download | bcm5719-llvm-5eed4e2664aa7187f46eb12e45a376d7ab7dd308.tar.gz bcm5719-llvm-5eed4e2664aa7187f46eb12e45a376d7ab7dd308.zip | |
AMDGPU/GlobalISel: Implement applyMappingImpl less incorrectly
We're checking the current register bank of the registers in the
instruction, but the mapping may have inserted cross bank copies and
is expecting to replace the registers.
We mostly get away with this currently, because VGPR->SGPR copies are
illegal, and we assume this won't happen. In a future change, we'll
start relying on more cross register bank copies being inserted, and
this starts to break down.
Diffstat (limited to 'llvm/lib/Target/Hexagon/HexagonDepTimingClasses.h')
0 files changed, 0 insertions, 0 deletions
