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authorKrzysztof Parzyszek <kparzysz@codeaurora.org>2018-12-05 20:18:09 +0000
committerKrzysztof Parzyszek <kparzysz@codeaurora.org>2018-12-05 20:18:09 +0000
commit13a9cf28a1202aa401aec5e0b90268e52d74c360 (patch)
tree881cea7a03a016be9fce8867b309dfecbfe04d1a /llvm/lib/Target/Hexagon/HexagonBitTracker.cpp
parentf75d4f329cc45542cac4eaa375bad84e0535f278 (diff)
downloadbcm5719-llvm-13a9cf28a1202aa401aec5e0b90268e52d74c360.tar.gz
bcm5719-llvm-13a9cf28a1202aa401aec5e0b90268e52d74c360.zip
[Hexagon] Foundation of support for Hexagon V66
llvm-svn: 348407
Diffstat (limited to 'llvm/lib/Target/Hexagon/HexagonBitTracker.cpp')
-rw-r--r--llvm/lib/Target/Hexagon/HexagonBitTracker.cpp15
1 files changed, 11 insertions, 4 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp b/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp
index 94aacbed6af..92b6da871a4 100644
--- a/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp
@@ -93,11 +93,12 @@ BT::BitMask HexagonEvaluator::mask(unsigned Reg, unsigned Sub) const {
const TargetRegisterClass &RC = *MRI.getRegClass(Reg);
unsigned ID = RC.getID();
uint16_t RW = getRegBitWidth(RegisterRef(Reg, Sub));
- auto &HRI = static_cast<const HexagonRegisterInfo&>(TRI);
+ const auto &HRI = static_cast<const HexagonRegisterInfo&>(TRI);
bool IsSubLo = (Sub == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo));
switch (ID) {
case Hexagon::DoubleRegsRegClassID:
case Hexagon::HvxWRRegClassID:
+ case Hexagon::HvxVQRRegClassID:
return IsSubLo ? BT::BitMask(0, RW-1)
: BT::BitMask(RW, 2*RW-1);
default:
@@ -114,9 +115,13 @@ uint16_t HexagonEvaluator::getPhysRegBitWidth(unsigned Reg) const {
assert(TargetRegisterInfo::isPhysicalRegister(Reg));
using namespace Hexagon;
- for (auto &RC : {HvxVRRegClass, HvxWRRegClass, HvxQRRegClass})
- if (RC.contains(Reg))
- return TRI.getRegSizeInBits(RC);
+ const auto &HST = MF.getSubtarget<HexagonSubtarget>();
+ if (HST.useHVXOps()) {
+ for (auto &RC : {HvxVRRegClass, HvxWRRegClass, HvxQRRegClass,
+ HvxVQRRegClass})
+ if (RC.contains(Reg))
+ return TRI.getRegSizeInBits(RC);
+ }
// Default treatment for other physical registers.
if (const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg))
return TRI.getRegSizeInBits(*RC);
@@ -142,6 +147,8 @@ const TargetRegisterClass &HexagonEvaluator::composeWithSubRegIndex(
return Hexagon::IntRegsRegClass;
case Hexagon::HvxWRRegClassID:
return Hexagon::HvxVRRegClass;
+ case Hexagon::HvxVQRRegClassID:
+ return Hexagon::HvxWRRegClass;
default:
break;
}
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