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| author | Francis Visoiu Mistrih <francisvm@yahoo.com> | 2017-11-28 12:42:37 +0000 |
|---|---|---|
| committer | Francis Visoiu Mistrih <francisvm@yahoo.com> | 2017-11-28 12:42:37 +0000 |
| commit | 9d419d3b0cfda0f85d88633bd8620cd65ccb0498 (patch) | |
| tree | e1fa028a9c3a8d514e67b9bac321519331979dea /llvm/lib/Target/Hexagon/BitTracker.cpp | |
| parent | 8dc603b03147c91ff4e66b8bfc934aad6c4cb4b3 (diff) | |
| download | bcm5719-llvm-9d419d3b0cfda0f85d88633bd8620cd65ccb0498.tar.gz bcm5719-llvm-9d419d3b0cfda0f85d88633bd8620cd65ccb0498.zip | |
[CodeGen] Rename functions PrintReg* to printReg*
LLVM Coding Standards:
Function names should be verb phrases (as they represent actions), and
command-like function should be imperative. The name should be camel
case, and start with a lower case letter (e.g. openFile() or isFoo()).
Differential Revision: https://reviews.llvm.org/D40416
llvm-svn: 319168
Diffstat (limited to 'llvm/lib/Target/Hexagon/BitTracker.cpp')
| -rw-r--r-- | llvm/lib/Target/Hexagon/BitTracker.cpp | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/llvm/lib/Target/Hexagon/BitTracker.cpp b/llvm/lib/Target/Hexagon/BitTracker.cpp index 39b567b9a25..5e20d8ca0fd 100644 --- a/llvm/lib/Target/Hexagon/BitTracker.cpp +++ b/llvm/lib/Target/Hexagon/BitTracker.cpp @@ -182,7 +182,7 @@ namespace llvm { void BitTracker::print_cells(raw_ostream &OS) const { for (const std::pair<unsigned, RegisterCell> P : Map) - dbgs() << PrintReg(P.first, &ME.TRI) << " -> " << P.second << "\n"; + dbgs() << printReg(P.first, &ME.TRI) << " -> " << P.second << "\n"; } BitTracker::BitTracker(const MachineEvaluator &E, MachineFunction &F) @@ -794,14 +794,14 @@ void BT::visitPHI(const MachineInstr &PI) { RegisterRef RU = PI.getOperand(i); RegisterCell ResC = ME.getCell(RU, Map); if (Trace) - dbgs() << " input reg: " << PrintReg(RU.Reg, &ME.TRI, RU.Sub) + dbgs() << " input reg: " << printReg(RU.Reg, &ME.TRI, RU.Sub) << " cell: " << ResC << "\n"; Changed |= DefC.meet(ResC, DefRR.Reg); } if (Changed) { if (Trace) - dbgs() << "Output: " << PrintReg(DefRR.Reg, &ME.TRI, DefRR.Sub) + dbgs() << "Output: " << printReg(DefRR.Reg, &ME.TRI, DefRR.Sub) << " cell: " << DefC << "\n"; ME.putCell(DefRR, DefC, Map); visitUsesOf(DefRR.Reg); @@ -826,13 +826,13 @@ void BT::visitNonBranch(const MachineInstr &MI) { if (!MO.isReg() || !MO.isUse()) continue; RegisterRef RU(MO); - dbgs() << " input reg: " << PrintReg(RU.Reg, &ME.TRI, RU.Sub) + dbgs() << " input reg: " << printReg(RU.Reg, &ME.TRI, RU.Sub) << " cell: " << ME.getCell(RU, Map) << "\n"; } dbgs() << "Outputs:\n"; for (const std::pair<unsigned, RegisterCell> &P : ResMap) { RegisterRef RD(P.first); - dbgs() << " " << PrintReg(P.first, &ME.TRI) << " cell: " + dbgs() << " " << printReg(P.first, &ME.TRI) << " cell: " << ME.getCell(RD, ResMap) << "\n"; } } @@ -949,7 +949,7 @@ void BT::visitBranchesFrom(const MachineInstr &BI) { void BT::visitUsesOf(unsigned Reg) { if (Trace) - dbgs() << "visiting uses of " << PrintReg(Reg, &ME.TRI) << "\n"; + dbgs() << "visiting uses of " << printReg(Reg, &ME.TRI) << "\n"; for (const MachineInstr &UseI : MRI.use_nodbg_instructions(Reg)) { if (!InstrExec.count(&UseI)) |
