Move some more instruction creation methods from RegisterInfo into InstrInfo.

llvm-svn: 45484

4 files changed, 196 insertions, 201 deletions

diff --git a/llvm/lib/Target/CellSPU/SPUInstrInfo.cpp b/llvm/lib/Target/CellSPU/SPUInstrInfo.cpp
index 5c520b46607..c7cbd9b3335 100644
--- a/llvm/lib/Target/CellSPU/SPUInstrInfo.cpp
+++ b/llvm/lib/Target/CellSPU/SPUInstrInfo.cpp
@@ -13,6 +13,7 @@
 
 #include "SPURegisterNames.h"
 #include "SPUInstrInfo.h"
+#include "SPUInstrBuilder.h"
 #include "SPUTargetMachine.h"
 #include "SPUGenInstrInfo.inc"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
@@ -188,7 +189,7 @@ void SPUInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
                                    const TargetRegisterClass *SrcRC) const
 {
   if (DestRC != SrcRC) {
-    cerr << "SPURegisterInfo::copyRegToReg(): DestRC != SrcRC not supported!\n";
+    cerr << "SPUInstrInfo::copyRegToReg(): DestRC != SrcRC not supported!\n";
     abort();
   }
 
@@ -217,3 +218,173 @@ void SPUInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
     abort();
   }
 }
+
+void
+SPUInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
+                                     MachineBasicBlock::iterator MI,
+                                     unsigned SrcReg, bool isKill, int FrameIdx,
+                                     const TargetRegisterClass *RC) const
+{
+  MachineOpCode opc;
+  if (RC == SPU::GPRCRegisterClass) {
+    opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
+      ? SPU::STQDr128
+      : SPU::STQXr128;
+  } else if (RC == SPU::R64CRegisterClass) {
+    opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
+      ? SPU::STQDr64
+      : SPU::STQXr64;
+  } else if (RC == SPU::R64FPRegisterClass) {
+    opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
+      ? SPU::STQDr64
+      : SPU::STQXr64;
+  } else if (RC == SPU::R32CRegisterClass) {
+    opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
+      ? SPU::STQDr32
+      : SPU::STQXr32;
+  } else if (RC == SPU::R32FPRegisterClass) {
+    opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
+      ? SPU::STQDr32
+      : SPU::STQXr32;
+  } else if (RC == SPU::R16CRegisterClass) {
+    opc = (FrameIdx < SPUFrameInfo::maxFrameOffset()) ?
+      SPU::STQDr16
+      : SPU::STQXr16;
+  } else {
+    assert(0 && "Unknown regclass!");
+    abort();
+  }
+
+  addFrameReference(BuildMI(MBB, MI, get(opc))
+                    .addReg(SrcReg, false, false, isKill), FrameIdx);
+}
+
+void SPUInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
+                                     bool isKill,
+                                     SmallVectorImpl<MachineOperand> &Addr,
+                                     const TargetRegisterClass *RC,
+                                     SmallVectorImpl<MachineInstr*> &NewMIs) const {
+  cerr << "storeRegToAddr() invoked!\n";
+  abort();
+
+  if (Addr[0].isFrameIndex()) {
+    /* do what storeRegToStackSlot does here */
+  } else {
+    unsigned Opc = 0;
+    if (RC == SPU::GPRCRegisterClass) {
+      /* Opc = PPC::STW; */
+    } else if (RC == SPU::R16CRegisterClass) {
+      /* Opc = PPC::STD; */
+    } else if (RC == SPU::R32CRegisterClass) {
+      /* Opc = PPC::STFD; */
+    } else if (RC == SPU::R32FPRegisterClass) {
+      /* Opc = PPC::STFD; */
+    } else if (RC == SPU::R64FPRegisterClass) {
+      /* Opc = PPC::STFS; */
+    } else if (RC == SPU::VECREGRegisterClass) {
+      /* Opc = PPC::STVX; */
+    } else {
+      assert(0 && "Unknown regclass!");
+      abort();
+    }
+    MachineInstrBuilder MIB = BuildMI(get(Opc))
+      .addReg(SrcReg, false, false, isKill);
+    for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
+      MachineOperand &MO = Addr[i];
+      if (MO.isRegister())
+        MIB.addReg(MO.getReg());
+      else if (MO.isImmediate())
+        MIB.addImm(MO.getImm());
+      else
+        MIB.addFrameIndex(MO.getIndex());
+    }
+    NewMIs.push_back(MIB);
+  }
+}
+
+void
+SPUInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
+                                        MachineBasicBlock::iterator MI,
+                                        unsigned DestReg, int FrameIdx,
+                                        const TargetRegisterClass *RC) const
+{
+  MachineOpCode opc;
+  if (RC == SPU::GPRCRegisterClass) {
+    opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
+      ? SPU::LQDr128
+      : SPU::LQXr128;
+  } else if (RC == SPU::R64CRegisterClass) {
+    opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
+      ? SPU::LQDr64
+      : SPU::LQXr64;
+  } else if (RC == SPU::R64FPRegisterClass) {
+    opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
+      ? SPU::LQDr64
+      : SPU::LQXr64;
+  } else if (RC == SPU::R32CRegisterClass) {
+    opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
+      ? SPU::LQDr32
+      : SPU::LQXr32;
+  } else if (RC == SPU::R32FPRegisterClass) {
+    opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
+      ? SPU::LQDr32
+      : SPU::LQXr32;
+  } else if (RC == SPU::R16CRegisterClass) {
+    opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
+      ? SPU::LQDr16
+      : SPU::LQXr16;
+  } else {
+    assert(0 && "Unknown regclass in loadRegFromStackSlot!");
+    abort();
+  }
+
+  addFrameReference(BuildMI(MBB, MI, get(opc)).addReg(DestReg), FrameIdx);
+}
+
+/*!
+  \note We are really pessimistic here about what kind of a load we're doing.
+ */
+void SPUInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
+                                      SmallVectorImpl<MachineOperand> &Addr,
+                                      const TargetRegisterClass *RC,
+                                      SmallVectorImpl<MachineInstr*> &NewMIs)
+    const {
+  cerr << "loadRegToAddr() invoked!\n";
+  abort();
+
+  if (Addr[0].isFrameIndex()) {
+    /* do what loadRegFromStackSlot does here... */
+  } else {
+    unsigned Opc = 0;
+    if (RC == SPU::R8CRegisterClass) {
+      /* do brilliance here */
+    } else if (RC == SPU::R16CRegisterClass) {
+      /* Opc = PPC::LWZ; */
+    } else if (RC == SPU::R32CRegisterClass) {
+      /* Opc = PPC::LD; */
+    } else if (RC == SPU::R32FPRegisterClass) {
+      /* Opc = PPC::LFD; */
+    } else if (RC == SPU::R64FPRegisterClass) {
+      /* Opc = PPC::LFS; */
+    } else if (RC == SPU::VECREGRegisterClass) {
+      /* Opc = PPC::LVX; */
+    } else if (RC == SPU::GPRCRegisterClass) {
+      /* Opc = something else! */
+    } else {
+      assert(0 && "Unknown regclass!");
+      abort();
+    }
+    MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
+    for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
+      MachineOperand &MO = Addr[i];
+      if (MO.isRegister())
+        MIB.addReg(MO.getReg());
+      else if (MO.isImmediate())
+        MIB.addImm(MO.getImm());
+      else
+        MIB.addFrameIndex(MO.getIndex());
+    }
+    NewMIs.push_back(MIB);
+  }
+}
+
diff --git a/llvm/lib/Target/CellSPU/SPUInstrInfo.h b/llvm/lib/Target/CellSPU/SPUInstrInfo.h
index 5132b3fa7ff..22581fc3150 100644
--- a/llvm/lib/Target/CellSPU/SPUInstrInfo.h
+++ b/llvm/lib/Target/CellSPU/SPUInstrInfo.h
@@ -51,6 +51,30 @@ namespace llvm {
                               unsigned DestReg, unsigned SrcReg,
                               const TargetRegisterClass *DestRC,
                               const TargetRegisterClass *SrcRC) const;
+    
+    //! Store a register to a stack slot, based on its register class.
+    virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
+                                     MachineBasicBlock::iterator MBBI,
+                                     unsigned SrcReg, bool isKill, int FrameIndex,
+                                     const TargetRegisterClass *RC) const;
+
+    //! Store a register to an address, based on its register class
+    virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
+			                          SmallVectorImpl<MachineOperand> &Addr,
+			                          const TargetRegisterClass *RC,
+			                          SmallVectorImpl<MachineInstr*> &NewMIs) const;
+
+    //! Load a register from a stack slot, based on its register class.
+    virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
+                                      MachineBasicBlock::iterator MBBI,
+                                      unsigned DestReg, int FrameIndex,
+                                      const TargetRegisterClass *RC) const;
+
+    //! Loqad a register from an address, based on its register class
+    virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
+				                         SmallVectorImpl<MachineOperand> &Addr,
+				                         const TargetRegisterClass *RC,
+				                         SmallVectorImpl<MachineInstr*> &NewMIs) const;
   };
 }
 
diff --git a/llvm/lib/Target/CellSPU/SPURegisterInfo.cpp b/llvm/lib/Target/CellSPU/SPURegisterInfo.cpp
index a05ab41902a..3a0565d9554 100644
--- a/llvm/lib/Target/CellSPU/SPURegisterInfo.cpp
+++ b/llvm/lib/Target/CellSPU/SPURegisterInfo.cpp
@@ -191,175 +191,6 @@ SPURegisterInfo::SPURegisterInfo(const SPUSubtarget &subtarget,
 {
 }
 
-void
-SPURegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
-                                     MachineBasicBlock::iterator MI,
-                                     unsigned SrcReg, bool isKill, int FrameIdx,
-                                     const TargetRegisterClass *RC) const
-{
-  MachineOpCode opc;
-  if (RC == SPU::GPRCRegisterClass) {
-    opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
-      ? SPU::STQDr128
-      : SPU::STQXr128;
-  } else if (RC == SPU::R64CRegisterClass) {
-    opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
-      ? SPU::STQDr64
-      : SPU::STQXr64;
-  } else if (RC == SPU::R64FPRegisterClass) {
-    opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
-      ? SPU::STQDr64
-      : SPU::STQXr64;
-  } else if (RC == SPU::R32CRegisterClass) {
-    opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
-      ? SPU::STQDr32
-      : SPU::STQXr32;
-  } else if (RC == SPU::R32FPRegisterClass) {
-    opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
-      ? SPU::STQDr32
-      : SPU::STQXr32;
-  } else if (RC == SPU::R16CRegisterClass) {
-    opc = (FrameIdx < SPUFrameInfo::maxFrameOffset()) ?
-      SPU::STQDr16
-      : SPU::STQXr16;
-  } else {
-    assert(0 && "Unknown regclass!");
-    abort();
-  }
-
-  addFrameReference(BuildMI(MBB, MI, TII.get(opc))
-                    .addReg(SrcReg, false, false, isKill), FrameIdx);
-}
-
-void SPURegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
-                                     bool isKill,
-                                     SmallVectorImpl<MachineOperand> &Addr,
-                                     const TargetRegisterClass *RC,
-                                     SmallVectorImpl<MachineInstr*> &NewMIs) const {
-  cerr << "storeRegToAddr() invoked!\n";
-  abort();
-
-  if (Addr[0].isFrameIndex()) {
-    /* do what storeRegToStackSlot does here */
-  } else {
-    unsigned Opc = 0;
-    if (RC == SPU::GPRCRegisterClass) {
-      /* Opc = PPC::STW; */
-    } else if (RC == SPU::R16CRegisterClass) {
-      /* Opc = PPC::STD; */
-    } else if (RC == SPU::R32CRegisterClass) {
-      /* Opc = PPC::STFD; */
-    } else if (RC == SPU::R32FPRegisterClass) {
-      /* Opc = PPC::STFD; */
-    } else if (RC == SPU::R64FPRegisterClass) {
-      /* Opc = PPC::STFS; */
-    } else if (RC == SPU::VECREGRegisterClass) {
-      /* Opc = PPC::STVX; */
-    } else {
-      assert(0 && "Unknown regclass!");
-      abort();
-    }
-    MachineInstrBuilder MIB = BuildMI(TII.get(Opc))
-      .addReg(SrcReg, false, false, isKill);
-    for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
-      MachineOperand &MO = Addr[i];
-      if (MO.isRegister())
-        MIB.addReg(MO.getReg());
-      else if (MO.isImmediate())
-        MIB.addImm(MO.getImm());
-      else
-        MIB.addFrameIndex(MO.getIndex());
-    }
-    NewMIs.push_back(MIB);
-  }
-}
-
-void
-SPURegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
-                                        MachineBasicBlock::iterator MI,
-                                        unsigned DestReg, int FrameIdx,
-                                        const TargetRegisterClass *RC) const
-{
-  MachineOpCode opc;
-  if (RC == SPU::GPRCRegisterClass) {
-    opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
-      ? SPU::LQDr128
-      : SPU::LQXr128;
-  } else if (RC == SPU::R64CRegisterClass) {
-    opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
-      ? SPU::LQDr64
-      : SPU::LQXr64;
-  } else if (RC == SPU::R64FPRegisterClass) {
-    opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
-      ? SPU::LQDr64
-      : SPU::LQXr64;
-  } else if (RC == SPU::R32CRegisterClass) {
-    opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
-      ? SPU::LQDr32
-      : SPU::LQXr32;
-  } else if (RC == SPU::R32FPRegisterClass) {
-    opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
-      ? SPU::LQDr32
-      : SPU::LQXr32;
-  } else if (RC == SPU::R16CRegisterClass) {
-    opc = (FrameIdx < SPUFrameInfo::maxFrameOffset())
-      ? SPU::LQDr16
-      : SPU::LQXr16;
-  } else {
-    assert(0 && "Unknown regclass in loadRegFromStackSlot!");
-    abort();
-  }
-
-  addFrameReference(BuildMI(MBB, MI, TII.get(opc)).addReg(DestReg), FrameIdx);
-}
-
-/*!
-  \note We are really pessimistic here about what kind of a load we're doing.
- */
-void SPURegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
-                                      SmallVectorImpl<MachineOperand> &Addr,
-                                      const TargetRegisterClass *RC,
-                                      SmallVectorImpl<MachineInstr*> &NewMIs)
-    const {
-  cerr << "loadRegToAddr() invoked!\n";
-  abort();
-
-  if (Addr[0].isFrameIndex()) {
-    /* do what loadRegFromStackSlot does here... */
-  } else {
-    unsigned Opc = 0;
-    if (RC == SPU::R8CRegisterClass) {
-      /* do brilliance here */
-    } else if (RC == SPU::R16CRegisterClass) {
-      /* Opc = PPC::LWZ; */
-    } else if (RC == SPU::R32CRegisterClass) {
-      /* Opc = PPC::LD; */
-    } else if (RC == SPU::R32FPRegisterClass) {
-      /* Opc = PPC::LFD; */
-    } else if (RC == SPU::R64FPRegisterClass) {
-      /* Opc = PPC::LFS; */
-    } else if (RC == SPU::VECREGRegisterClass) {
-      /* Opc = PPC::LVX; */
-    } else if (RC == SPU::GPRCRegisterClass) {
-      /* Opc = something else! */
-    } else {
-      assert(0 && "Unknown regclass!");
-      abort();
-    }
-    MachineInstrBuilder MIB = BuildMI(TII.get(Opc), DestReg);
-    for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
-      MachineOperand &MO = Addr[i];
-      if (MO.isRegister())
-        MIB.addReg(MO.getReg());
-      else if (MO.isImmediate())
-        MIB.addImm(MO.getImm());
-      else
-        MIB.addFrameIndex(MO.getIndex());
-    }
-    NewMIs.push_back(MIB);
-  }
-}
-
 void SPURegisterInfo::reMaterialize(MachineBasicBlock &MBB,
                                     MachineBasicBlock::iterator I,
                                     unsigned DestReg,
diff --git a/llvm/lib/Target/CellSPU/SPURegisterInfo.h b/llvm/lib/Target/CellSPU/SPURegisterInfo.h
index 382bfdd5477..c5df762513b 100644
--- a/llvm/lib/Target/CellSPU/SPURegisterInfo.h
+++ b/llvm/lib/Target/CellSPU/SPURegisterInfo.h
@@ -40,37 +40,6 @@ namespace llvm {
      */
     static unsigned getRegisterNumbering(unsigned RegEnum);
 
-    //! Store a register to a stack slot, based on its register class.
-    void storeRegToStackSlot(MachineBasicBlock &MBB,
-                             MachineBasicBlock::iterator MBBI,
-                             unsigned SrcReg, bool isKill, int FrameIndex,
-                             const TargetRegisterClass *RC) const;
-
-    //! Store a register to an address, based on its register class
-    void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
-			SmallVectorImpl<MachineOperand> &Addr,
-			const TargetRegisterClass *RC,
-			SmallVectorImpl<MachineInstr*> &NewMIs) const;
-
-    //! Load a register from a stack slot, based on its register class.
-    void loadRegFromStackSlot(MachineBasicBlock &MBB,
-                              MachineBasicBlock::iterator MBBI,
-                              unsigned DestReg, int FrameIndex,
-                              const TargetRegisterClass *RC) const;
-
-    //! Loqad a register from an address, based on its register class
-    virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
-				 SmallVectorImpl<MachineOperand> &Addr,
-				 const TargetRegisterClass *RC,
-				 SmallVectorImpl<MachineInstr*> &NewMIs) const;
-
-    //! Copy a register to another
-    void copyRegToReg(MachineBasicBlock &MBB,
-                      MachineBasicBlock::iterator MI,
-                      unsigned DestReg, unsigned SrcReg,
-                      const TargetRegisterClass *DestRC,
-                      const TargetRegisterClass *SrcRC) const;
-
     void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
 		       unsigned DestReg, const MachineInstr *Orig) const;