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| author | Nadav Rotem <nadav.rotem@intel.com> | 2011-10-04 12:05:35 +0000 |
|---|---|---|
| committer | Nadav Rotem <nadav.rotem@intel.com> | 2011-10-04 12:05:35 +0000 |
| commit | 3b309efe38e40f85c3101c2195ef741f7a12ac9c (patch) | |
| tree | 4c95ed6f7b88c322ce89e4fc96a9e89ceb9af1ee /llvm/lib/Target/CellSPU | |
| parent | 04001625e4def74456888a2a20753ad6db1ccbc1 (diff) | |
| download | bcm5719-llvm-3b309efe38e40f85c3101c2195ef741f7a12ac9c.tar.gz bcm5719-llvm-3b309efe38e40f85c3101c2195ef741f7a12ac9c.zip | |
Set operation actions to legal types only.
llvm-svn: 141075
Diffstat (limited to 'llvm/lib/Target/CellSPU')
| -rw-r--r-- | llvm/lib/Target/CellSPU/SPUISelLowering.cpp | 17 |
1 files changed, 9 insertions, 8 deletions
diff --git a/llvm/lib/Target/CellSPU/SPUISelLowering.cpp b/llvm/lib/Target/CellSPU/SPUISelLowering.cpp index 03bfb4ee71e..ac33111f74a 100644 --- a/llvm/lib/Target/CellSPU/SPUISelLowering.cpp +++ b/llvm/lib/Target/CellSPU/SPUISelLowering.cpp @@ -402,6 +402,9 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM) i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { MVT::SimpleValueType VT = (MVT::SimpleValueType)i; + // Set operation actions to legal types only. + if (!isTypeLegal(VT)) continue; + // add/sub are legal for all supported vector VT's. setOperationAction(ISD::ADD, VT, Legal); setOperationAction(ISD::SUB, VT, Legal); @@ -423,14 +426,12 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM) // Custom lower build_vector, constant pool spills, insert and // extract vector elements: - if (isTypeLegal(VT)) { - setOperationAction(ISD::BUILD_VECTOR, VT, Custom); - setOperationAction(ISD::ConstantPool, VT, Custom); - setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom); - setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); - setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); - setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); - } + setOperationAction(ISD::BUILD_VECTOR, VT, Custom); + setOperationAction(ISD::ConstantPool, VT, Custom); + setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom); + setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); + setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); + setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); } setOperationAction(ISD::AND, MVT::v16i8, Custom); |

