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| author | Dan Gohman <gohman@apple.com> | 2010-04-17 14:41:14 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2010-04-17 14:41:14 +0000 |
| commit | 31ae586c74b9c399d8c04c0e8effd61a4dcfd653 (patch) | |
| tree | 26e625294334ffac128a64635d02559fd100942e /llvm/lib/Target/CellSPU | |
| parent | 95c7c427aa1ce8065cf9f9fd043fe8b5e48375e1 (diff) | |
| download | bcm5719-llvm-31ae586c74b9c399d8c04c0e8effd61a4dcfd653.tar.gz bcm5719-llvm-31ae586c74b9c399d8c04c0e8effd61a4dcfd653.zip | |
Move per-function state out of TargetLowering subclasses and into
MachineFunctionInfo subclasses.
llvm-svn: 101634
Diffstat (limited to 'llvm/lib/Target/CellSPU')
| -rw-r--r-- | llvm/lib/Target/CellSPU/SPUISelLowering.cpp | 9 | ||||
| -rw-r--r-- | llvm/lib/Target/CellSPU/SPUMachineFunction.h | 8 |
2 files changed, 13 insertions, 4 deletions
diff --git a/llvm/lib/Target/CellSPU/SPUISelLowering.cpp b/llvm/lib/Target/CellSPU/SPUISelLowering.cpp index 49b4f7eef07..67e6cdbd0b5 100644 --- a/llvm/lib/Target/CellSPU/SPUISelLowering.cpp +++ b/llvm/lib/Target/CellSPU/SPUISelLowering.cpp @@ -15,6 +15,7 @@ #include "SPUISelLowering.h" #include "SPUTargetMachine.h" #include "SPUFrameInfo.h" +#include "SPUMachineFunction.h" #include "llvm/Constants.h" #include "llvm/Function.h" #include "llvm/Intrinsics.h" @@ -1009,6 +1010,7 @@ SPUTargetLowering::LowerFormalArguments(SDValue Chain, MachineFunction &MF = DAG.getMachineFunction(); MachineFrameInfo *MFI = MF.getFrameInfo(); MachineRegisterInfo &RegInfo = MF.getRegInfo(); + SPUFunctionInfo *FuncInfo = MF.getInfo<SPUFunctionInfo>(); const unsigned *ArgRegs = SPURegisterInfo::getArgRegs(); const unsigned NumArgRegs = SPURegisterInfo::getNumArgRegs(); @@ -1091,9 +1093,10 @@ SPUTargetLowering::LowerFormalArguments(SDValue Chain, // Create the frame slot for (; ArgRegIdx != NumArgRegs; ++ArgRegIdx) { - VarArgsFrameIndex = MFI->CreateFixedObject(StackSlotSize, ArgOffset, - true, false); - SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); + FuncInfo->setVarArgsFrameIndex( + MFI->CreateFixedObject(StackSlotSize, ArgOffset, + true, false)); + SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); unsigned VReg = MF.addLiveIn(ArgRegs[ArgRegIdx], &SPU::R32CRegClass); SDValue ArgVal = DAG.getRegister(VReg, MVT::v16i8); SDValue Store = DAG.getStore(Chain, dl, ArgVal, FIN, NULL, 0, diff --git a/llvm/lib/Target/CellSPU/SPUMachineFunction.h b/llvm/lib/Target/CellSPU/SPUMachineFunction.h index 6a66967bc05..3ef3ccbcaae 100644 --- a/llvm/lib/Target/CellSPU/SPUMachineFunction.h +++ b/llvm/lib/Target/CellSPU/SPUMachineFunction.h @@ -26,14 +26,20 @@ private: /// bool UsesLR; + // VarArgsFrameIndex - FrameIndex for start of varargs area. + int VarArgsFrameIndex; + public: SPUFunctionInfo(MachineFunction& MF) - : UsesLR(false) + : UsesLR(false), + VarArgsFrameIndex(0) {} void setUsesLR(bool U) { UsesLR = U; } bool usesLR() { return UsesLR; } + int getVarArgsFrameIndex() const { return VarArgsFrameIndex; } + void setVarArgsFrameIndex(int Index) { VarArgsFrameIndex = Index; } }; } // end of namespace llvm |
