diff options
author | Dan Gohman <gohman@apple.com> | 2008-07-07 23:14:23 +0000 |
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committer | Dan Gohman <gohman@apple.com> | 2008-07-07 23:14:23 +0000 |
commit | 3b46030375b309ac6e198664bbbf859884318084 (patch) | |
tree | 384b02de07f0f190d5753652f676f6c9a9a7d00c /llvm/lib/Target/CellSPU/SPUInstrInfo.cpp | |
parent | 7f8b6d5f8034a78638f9e82e42b6e647bed7106e (diff) | |
download | bcm5719-llvm-3b46030375b309ac6e198664bbbf859884318084.tar.gz bcm5719-llvm-3b46030375b309ac6e198664bbbf859884318084.zip |
Pool-allocation for MachineInstrs, MachineBasicBlocks, and
MachineMemOperands. The pools are owned by MachineFunctions.
This drastically reduces the number of calls to malloc/free made
during the "Emit" phase of scheduling, as well as later phases
in CodeGen. Combined with other changes, this speeds up the
"instruction selection" phase of CodeGen by 10% in some cases.
llvm-svn: 53212
Diffstat (limited to 'llvm/lib/Target/CellSPU/SPUInstrInfo.cpp')
-rw-r--r-- | llvm/lib/Target/CellSPU/SPUInstrInfo.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/CellSPU/SPUInstrInfo.cpp b/llvm/lib/Target/CellSPU/SPUInstrInfo.cpp index aef361105bf..3998b984b21 100644 --- a/llvm/lib/Target/CellSPU/SPUInstrInfo.cpp +++ b/llvm/lib/Target/CellSPU/SPUInstrInfo.cpp @@ -291,7 +291,7 @@ void SPUInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, assert(0 && "Unknown regclass!"); abort(); } - MachineInstrBuilder MIB = BuildMI(get(Opc)) + MachineInstrBuilder MIB = BuildMI(MF, get(Opc)) .addReg(SrcReg, false, false, isKill); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; @@ -378,7 +378,7 @@ void SPUInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, assert(0 && "Unknown regclass!"); abort(); } - MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg); + MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; if (MO.isRegister()) @@ -414,7 +414,7 @@ SPUInstrInfo::foldMemoryOperand(MachineFunction &MF, unsigned InReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); if (FrameIndex < SPUFrameInfo::maxFrameOffset()) { - NewMI = addFrameReference(BuildMI(TII.get(SPU::STQDr32)) + NewMI = addFrameReference(BuildMI(MF, TII.get(SPU::STQDr32)) .addReg(InReg, false, false, isKill), FrameIndex); } @@ -423,7 +423,7 @@ SPUInstrInfo::foldMemoryOperand(MachineFunction &MF, bool isDead = MI->getOperand(0).isDead(); Opc = (FrameIndex < SPUFrameInfo::maxFrameOffset()) ? SPU::STQDr32 : SPU::STQXr32; - NewMI = addFrameReference(BuildMI(TII.get(Opc)) + NewMI = addFrameReference(BuildMI(MF, TII.get(Opc)) .addReg(OutReg, true, false, false, isDead), FrameIndex); } } |