diff options
| author | Kalle Raiskila <kalle.raiskila@nokia.com> | 2010-06-21 15:08:16 +0000 |
|---|---|---|
| committer | Kalle Raiskila <kalle.raiskila@nokia.com> | 2010-06-21 15:08:16 +0000 |
| commit | 0ab5a02579db6fa3a72f6bf11725f91efd71b498 (patch) | |
| tree | 106bb60a600fc6c709561f2a87283e6869ca46cc /llvm/lib/Target/CellSPU/SPUInstrInfo.cpp | |
| parent | d7f50c118ab3e16de75dd49559dc431ce46c48a5 (diff) | |
| download | bcm5719-llvm-0ab5a02579db6fa3a72f6bf11725f91efd71b498.tar.gz bcm5719-llvm-0ab5a02579db6fa3a72f6bf11725f91efd71b498.zip | |
Mark the SPU 'lr' instruction to never have side effects.
This allows the fast regiser allocator to remove redundant
register moves.
Update a set of tests that depend on the register allocator
to be linear scan.
llvm-svn: 106420
Diffstat (limited to 'llvm/lib/Target/CellSPU/SPUInstrInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/CellSPU/SPUInstrInfo.cpp | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/llvm/lib/Target/CellSPU/SPUInstrInfo.cpp b/llvm/lib/Target/CellSPU/SPUInstrInfo.cpp index 877d1c5dca3..9dfe01476c8 100644 --- a/llvm/lib/Target/CellSPU/SPUInstrInfo.cpp +++ b/llvm/lib/Target/CellSPU/SPUInstrInfo.cpp @@ -164,11 +164,9 @@ SPUInstrInfo::isMoveInstr(const MachineInstr& MI, MI.getOperand(0).isReg() && MI.getOperand(1).isReg() && "invalid SPU OR<type>_<vec> or LR instruction!"); - if (MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) { sourceReg = MI.getOperand(1).getReg(); destReg = MI.getOperand(0).getReg(); return true; - } break; } case SPU::ORv16i8: |
