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author | Nadav Rotem <nadav.rotem@intel.com> | 2011-10-16 10:02:06 +0000 |
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committer | Nadav Rotem <nadav.rotem@intel.com> | 2011-10-16 10:02:06 +0000 |
commit | bc25b6eb67955a48f012e1cca50a08cc83685182 (patch) | |
tree | 12c90b5aa11905b722229ddd7188a1f0a4d7ec84 /llvm/lib/Target/CellSPU/SPUISelLowering.cpp | |
parent | 454de773e16061435f860ccee81a4bfb6e2e1ec0 (diff) | |
download | bcm5719-llvm-bc25b6eb67955a48f012e1cca50a08cc83685182.tar.gz bcm5719-llvm-bc25b6eb67955a48f012e1cca50a08cc83685182.zip |
Fix a bug in LowerV2I64Splat, which generated a BUILD_VECTOR for which there was
no pattern.
llvm-svn: 142130
Diffstat (limited to 'llvm/lib/Target/CellSPU/SPUISelLowering.cpp')
-rw-r--r-- | llvm/lib/Target/CellSPU/SPUISelLowering.cpp | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/llvm/lib/Target/CellSPU/SPUISelLowering.cpp b/llvm/lib/Target/CellSPU/SPUISelLowering.cpp index 19327d8acf4..08ebb9291e4 100644 --- a/llvm/lib/Target/CellSPU/SPUISelLowering.cpp +++ b/llvm/lib/Target/CellSPU/SPUISelLowering.cpp @@ -1752,9 +1752,11 @@ SPU::LowerV2I64Splat(EVT OpVT, SelectionDAG& DAG, uint64_t SplatVal, // Both upper and lower are special, lower to a constant pool load: if (lower_special && upper_special) { - SDValue SplatValCN = DAG.getConstant(SplatVal, MVT::i64); - return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, - SplatValCN, SplatValCN); + SDValue UpperVal = DAG.getConstant(upper, MVT::i32); + SDValue LowerVal = DAG.getConstant(lower, MVT::i32); + SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, + UpperVal, LowerVal, UpperVal, LowerVal); + return DAG.getNode(ISD::BITCAST, dl, OpVT, BV); } SDValue LO32; |