CellSPU:

- Ensure that (operation) legalization emits proper FDIV libcall when needed.
- Fix various bugs encountered during llvm-spu-gcc build, along with various
  cleanups.
- Start supporting double precision comparisons for remaining libgcc2 build.
  Discovered interesting DAGCombiner feature, which is currently solved via
  custom lowering (64-bit constants are not legal on CellSPU, but DAGCombiner
  insists on inserting one anyway.)
- Update README.

llvm-svn: 62664

1 files changed, 36 insertions, 15 deletions

diff --git a/llvm/lib/Target/CellSPU/SPUISelDAGToDAG.cpp b/llvm/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
index 816502d9f58..0fc7aec9906 100644
--- a/llvm/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
@@ -685,26 +685,26 @@ SPUDAGToDAGISel::Select(SDValue Op) {
       break;
     case MVT::i32:
       shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, MVT::v4i32,
-                             CurDAG->getConstant(0x80808080, MVT::i32),
-                             CurDAG->getConstant(0x00010203, MVT::i32),
-                             CurDAG->getConstant(0x80808080, MVT::i32),
-                             CurDAG->getConstant(0x08090a0b, MVT::i32));
+                                 CurDAG->getConstant(0x80808080, MVT::i32),
+                                 CurDAG->getConstant(0x00010203, MVT::i32),
+                                 CurDAG->getConstant(0x80808080, MVT::i32),
+                                 CurDAG->getConstant(0x08090a0b, MVT::i32));
       break;
 
     case MVT::i16:
       shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, MVT::v4i32,
-                             CurDAG->getConstant(0x80808080, MVT::i32),
-                             CurDAG->getConstant(0x80800203, MVT::i32),
-                             CurDAG->getConstant(0x80808080, MVT::i32),
-                             CurDAG->getConstant(0x80800a0b, MVT::i32));
+                                 CurDAG->getConstant(0x80808080, MVT::i32),
+                                 CurDAG->getConstant(0x80800203, MVT::i32),
+                                 CurDAG->getConstant(0x80808080, MVT::i32),
+                                 CurDAG->getConstant(0x80800a0b, MVT::i32));
       break;
 
     case MVT::i8:
       shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, MVT::v4i32,
-                             CurDAG->getConstant(0x80808080, MVT::i32),
-                             CurDAG->getConstant(0x80808003, MVT::i32),
-                             CurDAG->getConstant(0x80808080, MVT::i32),
-                             CurDAG->getConstant(0x8080800b, MVT::i32));
+                                 CurDAG->getConstant(0x80808080, MVT::i32),
+                                 CurDAG->getConstant(0x80808003, MVT::i32),
+                                 CurDAG->getConstant(0x80808080, MVT::i32),
+                                 CurDAG->getConstant(0x8080800b, MVT::i32));
       break;
     }
 
@@ -714,9 +714,9 @@ SPUDAGToDAGISel::Select(SDValue Op) {
 
     SDValue zextShuffle =
             CurDAG->getNode(SPUISD::SHUFB, OpVecVT,
-                                       SDValue(PromoteScalar, 0),
-                                       SDValue(PromoteScalar, 0),
-                                       SDValue(shufMaskLoad, 0));
+                            SDValue(PromoteScalar, 0),
+                            SDValue(PromoteScalar, 0),
+                            SDValue(shufMaskLoad, 0));
 
     // N.B.: BIT_CONVERT replaces and updates the zextShuffle node, so we
     // re-use it in the VEC2PREFSLOT selection without needing to explicitly
@@ -745,6 +745,27 @@ SPUDAGToDAGISel::Select(SDValue Op) {
     return SelectCode(CurDAG->getNode(SPUISD::MUL64_MARKER, OpVT,
                                       Op.getOperand(0), Op.getOperand(1),
                                       SDValue(CGLoad, 0)));
+  } else if (Opc == ISD::ADD && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
+    SDNode *CGLoad =
+            emitBuildVector(SPU::getCarryGenerateShufMask(*CurDAG));
+
+    return SelectCode(CurDAG->getNode(SPUISD::ADD64_MARKER, OpVT,
+                                      Op.getOperand(0), Op.getOperand(1),
+                                      SDValue(CGLoad, 0)));
+  } else if (Opc == ISD::SUB && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
+    SDNode *CGLoad =
+            emitBuildVector(SPU::getBorrowGenerateShufMask(*CurDAG));
+
+    return SelectCode(CurDAG->getNode(SPUISD::SUB64_MARKER, OpVT,
+                                      Op.getOperand(0), Op.getOperand(1),
+                                      SDValue(CGLoad, 0)));
+  } else if (Opc == ISD::MUL && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
+    SDNode *CGLoad =
+            emitBuildVector(SPU::getCarryGenerateShufMask(*CurDAG));
+
+    return SelectCode(CurDAG->getNode(SPUISD::MUL64_MARKER, OpVT,
+                                      Op.getOperand(0), Op.getOperand(1),
+                                      SDValue(CGLoad, 0)));
   } else if (Opc == ISD::SHL) {
     if (OpVT == MVT::i64) {
       return SelectSHLi64(Op, OpVT);