Changes to support making the shift instructions be true BinaryOperators.

This feature is needed in order to support shifts of more than 255 bits
on large integer types.  This changes the syntax for llvm assembly to
make shl, ashr and lshr instructions look like a binary operator:
   shl i32 %X, 1
instead of
   shl i32 %X, i8 1
Additionally, this should help a few passes perform additional optimizations.

llvm-svn: 33776

1 files changed, 8 insertions, 9 deletions

diff --git a/llvm/lib/Target/CBackend/CBackend.cpp b/llvm/lib/Target/CBackend/CBackend.cpp
index 785e7643e4f..6116bcdd765 100644
--- a/llvm/lib/Target/CBackend/CBackend.cpp
+++ b/llvm/lib/Target/CBackend/CBackend.cpp
@@ -225,7 +225,6 @@ namespace {
     void visitSelectInst(SelectInst &I);
     void visitCallInst (CallInst &I);
     void visitInlineAsm(CallInst &I);
-    void visitShiftInst(ShiftInst &I) { visitBinaryOperator(I); }
 
     void visitMallocInst(MallocInst &I);
     void visitAllocaInst(AllocaInst &I);
@@ -2160,18 +2159,18 @@ void CWriter::visitBinaryOperator(Instruction &I) {
     writeOperandWithCast(I.getOperand(0), I.getOpcode());
 
     switch (I.getOpcode()) {
-    case Instruction::Add: Out << " + "; break;
-    case Instruction::Sub: Out << " - "; break;
-    case Instruction::Mul: Out << '*'; break;
+    case Instruction::Add:  Out << " + "; break;
+    case Instruction::Sub:  Out << " - "; break;
+    case Instruction::Mul:  Out << " * "; break;
     case Instruction::URem:
     case Instruction::SRem:
-    case Instruction::FRem: Out << '%'; break;
+    case Instruction::FRem: Out << " % "; break;
     case Instruction::UDiv:
     case Instruction::SDiv: 
-    case Instruction::FDiv: Out << '/'; break;
-    case Instruction::And: Out << " & "; break;
-    case Instruction::Or: Out << " | "; break;
-    case Instruction::Xor: Out << " ^ "; break;
+    case Instruction::FDiv: Out << " / "; break;
+    case Instruction::And:  Out << " & "; break;
+    case Instruction::Or:   Out << " | "; break;
+    case Instruction::Xor:  Out << " ^ "; break;
     case Instruction::Shl : Out << " << "; break;
     case Instruction::LShr:
     case Instruction::AShr: Out << " >> "; break;