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author | Francis Visoiu Mistrih <francisvm@yahoo.com> | 2017-11-30 12:12:19 +0000 |
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committer | Francis Visoiu Mistrih <francisvm@yahoo.com> | 2017-11-30 12:12:19 +0000 |
commit | 93ef145862e140ed880fd2eca404dc2641a12093 (patch) | |
tree | 6e29f9874fc995008ef8e53a6375b06de67d33e6 /llvm/lib/Target/BPF | |
parent | bfb8fa5a160a943d9cf8d7254cf4375f2c135f2d (diff) | |
download | bcm5719-llvm-93ef145862e140ed880fd2eca404dc2641a12093.tar.gz bcm5719-llvm-93ef145862e140ed880fd2eca404dc2641a12093.zip |
[CodeGen] Print "%vreg0" as "%0" in both MIR and debug output
As part of the unification of the debug format and the MIR format, avoid
printing "vreg" for virtual registers (which is one of the current MIR
possibilities).
Basically:
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/%vreg([0-9]+)/%\1/g"
* grep -nr '%vreg' . and fix if needed
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/ vreg([0-9]+)/ %\1/g"
* grep -nr 'vreg[0-9]\+' . and fix if needed
Differential Revision: https://reviews.llvm.org/D40420
llvm-svn: 319427
Diffstat (limited to 'llvm/lib/Target/BPF')
-rw-r--r-- | llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp b/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp index 1c12c23c931..ef52bae3d76 100644 --- a/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp +++ b/llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp @@ -546,7 +546,7 @@ void BPFDAGToDAGISel::PreprocessTrunc(SDNode *Node, if (!RegN || !TargetRegisterInfo::isVirtualRegister(RegN->getReg())) return; unsigned AndOpReg = RegN->getReg(); - DEBUG(dbgs() << "Examine %vreg" << TargetRegisterInfo::virtReg2Index(AndOpReg) + DEBUG(dbgs() << "Examine %" << TargetRegisterInfo::virtReg2Index(AndOpReg) << '\n'); // Examine the PHI insns in the MachineBasicBlock to found out the @@ -574,9 +574,9 @@ void BPFDAGToDAGISel::PreprocessTrunc(SDNode *Node, return; } else { // The PHI node looks like: - // %vreg2<def> = PHI %vreg0, <BB#1>, %vreg1, <BB#3> - // Trace each incoming definition, e.g., (%vreg0, BB#1) and (%vreg1, BB#3) - // The AND operation can be removed if both %vreg0 in BB#1 and %vreg1 in + // %2<def> = PHI %0, <BB#1>, %1, <BB#3> + // Trace each incoming definition, e.g., (%0, BB#1) and (%1, BB#3) + // The AND operation can be removed if both %0 in BB#1 and %1 in // BB#3 are defined with with a load matching the MaskN. DEBUG(dbgs() << "Check PHI Insn: "; MII->dump(); dbgs() << '\n'); unsigned PrevReg = -1; |