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| author | Yonghong Song <yhs@fb.com> | 2018-02-23 23:49:19 +0000 |
|---|---|---|
| committer | Yonghong Song <yhs@fb.com> | 2018-02-23 23:49:19 +0000 |
| commit | 3a564a8f6e9b60553ad4b7bebeee1ec8065b2a0f (patch) | |
| tree | cb47c20d7ce5868f61c91296f1449440db738845 /llvm/lib/Target/BPF | |
| parent | ec84e2f1b08c297f82f517bc5c904dee78c2a6bc (diff) | |
| download | bcm5719-llvm-3a564a8f6e9b60553ad4b7bebeee1ec8065b2a0f.tar.gz bcm5719-llvm-3a564a8f6e9b60553ad4b7bebeee1ec8065b2a0f.zip | |
bpf: Tighten the immediate predication for 32-bit alu instructions
These 32-bit ALU insn patterns which takes immediate as one operand were
initially added to enable AsmParser support, and the AsmMatcher uses "ins"
and "outs" fields to deduct the operand constraint.
However, the instruction selector doesn't work the same as AsmMatcher. The
selector will use the "pattern" field for which we are not setting the
predication for immediate operands correctly.
Without this patch, i32 would eventually means all i32 operands are valid,
both imm and gpr, while these patterns should allow imm only.
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
Reviewed-by: Yonghong Song <yhs@fb.com>
llvm-svn: 325980
Diffstat (limited to 'llvm/lib/Target/BPF')
| -rw-r--r-- | llvm/lib/Target/BPF/BPFInstrInfo.td | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/llvm/lib/Target/BPF/BPFInstrInfo.td b/llvm/lib/Target/BPF/BPFInstrInfo.td index 3634f2c38b7..d4f9c488f67 100644 --- a/llvm/lib/Target/BPF/BPFInstrInfo.td +++ b/llvm/lib/Target/BPF/BPFInstrInfo.td @@ -57,6 +57,8 @@ def u64imm : Operand<i64> { def i64immSExt32 : PatLeaf<(i64 imm), [{return isInt<32>(N->getSExtValue()); }]>; +def i32immSExt32 : PatLeaf<(i32 imm), + [{return isInt<32>(N->getSExtValue()); }]>; // Addressing modes. def ADDRri : ComplexPattern<i64, 2, "SelectAddr", [], []>; @@ -218,7 +220,7 @@ multiclass ALU<BPFArithOp Opc, string OpcodeStr, SDNode OpNode> { (outs GPR32:$dst), (ins GPR32:$src2, i32imm:$imm), "$dst "#OpcodeStr#" $imm", - [(set GPR32:$dst, (OpNode GPR32:$src2, i32:$imm))]>; + [(set GPR32:$dst, (OpNode GPR32:$src2, i32immSExt32:$imm))]>; } let Constraints = "$dst = $src2" in { @@ -292,7 +294,7 @@ def MOV_ri_32 : ALU_RI<BPF_ALU, BPF_MOV, (outs GPR32:$dst), (ins i32imm:$imm), "$dst = $imm", - [(set GPR32:$dst, (i32 i32:$imm))]>; + [(set GPR32:$dst, (i32 i32immSExt32:$imm))]>; } def FI_ri |
