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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-09-10 11:49:23 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2018-09-10 11:49:23 +0000 |
| commit | 57b5966dad858f30fd3bbdf42ba560ef9382f0c2 (patch) | |
| tree | 6f5385281a1576628bdfbf20d7f08daf9e40157d /llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp | |
| parent | 38a889c1853c1831a1b3eef07122415645582fac (diff) | |
| download | bcm5719-llvm-57b5966dad858f30fd3bbdf42ba560ef9382f0c2.tar.gz bcm5719-llvm-57b5966dad858f30fd3bbdf42ba560ef9382f0c2.zip | |
DAG: Handle odd vector sizes in calling conv splitting
This already worked if only one register piece was used,
but didn't if a type was split into multiple, unequal
sized pieces.
Fixes not splitting 3i16/v3f16 into two registers for
AMDGPU.
This will also allow fixing the ABI for 16-bit vectors
in a future commit so that it's the same for all subtargets.
llvm-svn: 341801
Diffstat (limited to 'llvm/lib/Target/BPF/Disassembler/BPFDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions
