summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/Alpha/AlphaTargetMachine.cpp
diff options
context:
space:
mode:
authorAndrew Lenharth <andrewl@lenharth.org>2005-03-02 17:21:38 +0000
committerAndrew Lenharth <andrewl@lenharth.org>2005-03-02 17:21:38 +0000
commited4b6488a706dc4302f1b64d5d61915c59e427f6 (patch)
tree4ef403d4041dbad3206cb6157cfb601dd4c2d980 /llvm/lib/Target/Alpha/AlphaTargetMachine.cpp
parentc8bb99760ae1be2b54ab05ab947298aedba06e65 (diff)
downloadbcm5719-llvm-ed4b6488a706dc4302f1b64d5d61915c59e427f6.tar.gz
bcm5719-llvm-ed4b6488a706dc4302f1b64d5d61915c59e427f6.zip
Added LSR as a beta pass for alpha
llvm-svn: 20407
Diffstat (limited to 'llvm/lib/Target/Alpha/AlphaTargetMachine.cpp')
-rw-r--r--llvm/lib/Target/Alpha/AlphaTargetMachine.cpp9
1 files changed, 9 insertions, 0 deletions
diff --git a/llvm/lib/Target/Alpha/AlphaTargetMachine.cpp b/llvm/lib/Target/Alpha/AlphaTargetMachine.cpp
index b077f074481..80a88662a12 100644
--- a/llvm/lib/Target/Alpha/AlphaTargetMachine.cpp
+++ b/llvm/lib/Target/Alpha/AlphaTargetMachine.cpp
@@ -26,6 +26,12 @@ namespace {
RegisterTarget<AlphaTargetMachine> X("alpha", " Alpha (incomplete)");
}
+namespace llvm {
+ cl::opt<bool> EnableAlphaLSR("enable-lsr-for-alpha",
+ cl::desc("Enable LSR for Alpha (beta option!)"),
+ cl::Hidden);
+}
+
unsigned AlphaTargetMachine::getModuleMatchQuality(const Module &M) {
// We strongly match "alpha*".
std::string TT = M.getTargetTriple();
@@ -54,6 +60,9 @@ AlphaTargetMachine::AlphaTargetMachine( const Module &M, IntrinsicLowering *IL)
bool AlphaTargetMachine::addPassesToEmitAssembly(PassManager &PM,
std::ostream &Out) {
+ if (EnableAlphaLSR)
+ PM.add(createLoopStrengthReducePass());
+
// FIXME: Implement efficient support for garbage collection intrinsics.
PM.add(createLowerGCPass());
OpenPOWER on IntegriCloud