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| author | Andrew Lenharth <andrewl@lenharth.org> | 2005-03-03 19:03:21 +0000 |
|---|---|---|
| committer | Andrew Lenharth <andrewl@lenharth.org> | 2005-03-03 19:03:21 +0000 |
| commit | 00348ce902fc26c84671fe02255263fe38c6619e (patch) | |
| tree | 73ccd0e2d607addcfbaf9778b3000f04d85bff76 /llvm/lib/Target/Alpha/AlphaTargetMachine.cpp | |
| parent | 1a678c67c9e5208a9ea3aacd35fcf520bb81cd3b (diff) | |
| download | bcm5719-llvm-00348ce902fc26c84671fe02255263fe38c6619e.tar.gz bcm5719-llvm-00348ce902fc26c84671fe02255263fe38c6619e.zip | |
LSR cleanup patch
llvm-svn: 20422
Diffstat (limited to 'llvm/lib/Target/Alpha/AlphaTargetMachine.cpp')
| -rw-r--r-- | llvm/lib/Target/Alpha/AlphaTargetMachine.cpp | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/llvm/lib/Target/Alpha/AlphaTargetMachine.cpp b/llvm/lib/Target/Alpha/AlphaTargetMachine.cpp index 80a88662a12..7bc4852105d 100644 --- a/llvm/lib/Target/Alpha/AlphaTargetMachine.cpp +++ b/llvm/lib/Target/Alpha/AlphaTargetMachine.cpp @@ -60,8 +60,10 @@ AlphaTargetMachine::AlphaTargetMachine( const Module &M, IntrinsicLowering *IL) bool AlphaTargetMachine::addPassesToEmitAssembly(PassManager &PM, std::ostream &Out) { - if (EnableAlphaLSR) + if (EnableAlphaLSR) { PM.add(createLoopStrengthReducePass()); + PM.add(createCFGSimplificationPass()); + } // FIXME: Implement efficient support for garbage collection intrinsics. PM.add(createLowerGCPass()); |
