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authorChris Lattner <sabre@nondot.org>2005-09-30 01:29:42 +0000
committerChris Lattner <sabre@nondot.org>2005-09-30 01:29:42 +0000
commita654525c1c9f926c4430bcdfe11852e4f5a9bbba (patch)
tree99cb4423a68b4659c46851814dc487f9577c9365 /llvm/lib/Target/Alpha/AlphaRegisterInfo.h
parent5a6199f3872af8dd9eecea7529dd7cb12ee59958 (diff)
downloadbcm5719-llvm-a654525c1c9f926c4430bcdfe11852e4f5a9bbba.tar.gz
bcm5719-llvm-a654525c1c9f926c4430bcdfe11852e4f5a9bbba.zip
Pass extra regclasses into spilling code
llvm-svn: 23537
Diffstat (limited to 'llvm/lib/Target/Alpha/AlphaRegisterInfo.h')
-rw-r--r--llvm/lib/Target/Alpha/AlphaRegisterInfo.h6
1 files changed, 4 insertions, 2 deletions
diff --git a/llvm/lib/Target/Alpha/AlphaRegisterInfo.h b/llvm/lib/Target/Alpha/AlphaRegisterInfo.h
index d755432321b..0d8c24a50e7 100644
--- a/llvm/lib/Target/Alpha/AlphaRegisterInfo.h
+++ b/llvm/lib/Target/Alpha/AlphaRegisterInfo.h
@@ -27,11 +27,13 @@ struct AlphaRegisterInfo : public AlphaGenRegisterInfo {
/// Code Generation virtual methods...
void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
- unsigned SrcReg, int FrameIndex) const;
+ unsigned SrcReg, int FrameIndex,
+ const TargetRegisterClass *RC) const;
void loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
- unsigned DestReg, int FrameIndex) const;
+ unsigned DestReg, int FrameIndex,
+ const TargetRegisterClass *RC) const;
void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
unsigned DestReg, unsigned SrcReg,
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