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author | Evan Cheng <evan.cheng@apple.com> | 2006-11-13 23:36:35 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2006-11-13 23:36:35 +0000 |
commit | dbd3d294e6dec8928f56975b19b91c8772d7f937 (patch) | |
tree | 61b8f3847f6b516ef35c93c05a3e7b389c4b1cbf /llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp | |
parent | 77af6ac5e869e05ce3d49e22ea1b022ee9c6564b (diff) | |
download | bcm5719-llvm-dbd3d294e6dec8928f56975b19b91c8772d7f937.tar.gz bcm5719-llvm-dbd3d294e6dec8928f56975b19b91c8772d7f937.zip |
Matches MachineInstr changes.
llvm-svn: 31712
Diffstat (limited to 'llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp')
-rw-r--r-- | llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp b/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp index cc6c108420d..6be5e074a39 100644 --- a/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp +++ b/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp @@ -51,8 +51,9 @@ static long getLower16(long l) return l - h * IMM_MULT; } -AlphaRegisterInfo::AlphaRegisterInfo() - : AlphaGenRegisterInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP) +AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii) + : AlphaGenRegisterInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP), + TII(tii) { } @@ -114,13 +115,13 @@ MachineInstr *AlphaRegisterInfo::foldMemoryOperand(MachineInstr *MI, unsigned InReg = MI->getOperand(1).getReg(); Opc = (Opc == Alpha::BISr) ? Alpha::STQ : ((Opc == Alpha::CPYSS) ? Alpha::STS : Alpha::STT); - return BuildMI(Opc, 3).addReg(InReg).addFrameIndex(FrameIndex) + return BuildMI(TII, Opc, 3).addReg(InReg).addFrameIndex(FrameIndex) .addReg(Alpha::F31); } else { // load -> move unsigned OutReg = MI->getOperand(0).getReg(); Opc = (Opc == Alpha::BISr) ? Alpha::LDQ : ((Opc == Alpha::CPYSS) ? Alpha::LDS : Alpha::LDT); - return BuildMI(Opc, 2, OutReg).addFrameIndex(FrameIndex) + return BuildMI(TII, Opc, 2, OutReg).addFrameIndex(FrameIndex) .addReg(Alpha::F31); } } @@ -205,11 +206,11 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineInstr *New; if (Old->getOpcode() == Alpha::ADJUSTSTACKDOWN) { - New=BuildMI(Alpha::LDA, 2, Alpha::R30) + New=BuildMI(TII, Alpha::LDA, 2, Alpha::R30) .addImm(-Amount).addReg(Alpha::R30); } else { assert(Old->getOpcode() == Alpha::ADJUSTSTACKUP); - New=BuildMI(Alpha::LDA, 2, Alpha::R30) + New=BuildMI(TII, Alpha::LDA, 2, Alpha::R30) .addImm(Amount).addReg(Alpha::R30); } @@ -266,7 +267,7 @@ AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const { MI.getOperand(i + 1).ChangeToRegister(Alpha::R28, false); MI.getOperand(i).ChangeToImmediate(getLower16(Offset)); //insert the new - MachineInstr* nMI=BuildMI(Alpha::LDAH, 2, Alpha::R28) + MachineInstr* nMI=BuildMI(TII, Alpha::LDAH, 2, Alpha::R28) .addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30); MBB.insert(II, nMI); } else { |