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authorAndrew Lenharth <andrewl@lenharth.org>2005-02-01 20:35:57 +0000
committerAndrew Lenharth <andrewl@lenharth.org>2005-02-01 20:35:57 +0000
commitc777d4f03d64b688ef1f8e7437955ebfc032f585 (patch)
tree17f3e42b7fa370cf0001ee65893a15cc4ec84694 /llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
parent8fb0d5002b4d3b7f9e7ada27c9e0c0fd44219d92 (diff)
downloadbcm5719-llvm-c777d4f03d64b688ef1f8e7437955ebfc032f585.tar.gz
bcm5719-llvm-c777d4f03d64b688ef1f8e7437955ebfc032f585.zip
Correct stack stuff for FP
llvm-svn: 19973
Diffstat (limited to 'llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp')
-rw-r--r--llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp17
1 files changed, 12 insertions, 5 deletions
diff --git a/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp b/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
index 055bf14d910..bd38fd40806 100644
--- a/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
+++ b/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp
@@ -49,8 +49,12 @@ AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
unsigned SrcReg, int FrameIdx) const {
//std::cerr << "Trying to store " << getPrettyName(SrcReg) << " to " << FrameIdx << "\n";
//BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg);
- BuildMI(MBB, MI, Alpha::STQ, 3).addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
- // assert(0 && "TODO");
+ if (getClass(SrcReg) == Alpha::FPRCRegisterClass)
+ BuildMI(MBB, MI, Alpha::STT, 3).addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
+ else if (getClass(SrcReg) == Alpha::GPRCRegisterClass)
+ BuildMI(MBB, MI, Alpha::STQ, 3).addReg(SrcReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
+ else
+ abort();
}
void
@@ -58,9 +62,12 @@ AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, int FrameIdx) const{
//std::cerr << "Trying to load " << getPrettyName(DestReg) << " to " << FrameIdx << "\n";
- //BuildMI(MBB, MI, Alpha::WTF, 0, DestReg);
- BuildMI(MBB, MI, Alpha::LDQ, 2, DestReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
- // assert(0 && "TODO");
+ if (getClass(DestReg) == Alpha::FPRCRegisterClass)
+ BuildMI(MBB, MI, Alpha::LDT, 2, DestReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
+ else if (getClass(DestReg) == Alpha::GPRCRegisterClass)
+ BuildMI(MBB, MI, Alpha::LDQ, 2, DestReg).addFrameIndex(FrameIdx).addReg(Alpha::F31);
+ else
+ abort();
}
void AlphaRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
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