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| author | Chris Lattner <sabre@nondot.org> | 2005-09-30 01:29:42 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2005-09-30 01:29:42 +0000 |
| commit | a654525c1c9f926c4430bcdfe11852e4f5a9bbba (patch) | |
| tree | 99cb4423a68b4659c46851814dc487f9577c9365 /llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp | |
| parent | 5a6199f3872af8dd9eecea7529dd7cb12ee59958 (diff) | |
| download | bcm5719-llvm-a654525c1c9f926c4430bcdfe11852e4f5a9bbba.tar.gz bcm5719-llvm-a654525c1c9f926c4430bcdfe11852e4f5a9bbba.zip | |
Pass extra regclasses into spilling code
llvm-svn: 23537
Diffstat (limited to 'llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp b/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp index b6c93531c99..ac7d3f146f8 100644 --- a/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp +++ b/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp @@ -75,7 +75,8 @@ static const TargetRegisterClass *getClass(unsigned SrcReg) { void AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, - unsigned SrcReg, int FrameIdx) const { + unsigned SrcReg, int FrameIdx, + const TargetRegisterClass *RC) const { //std::cerr << "Trying to store " << getPrettyName(SrcReg) << " to " << FrameIdx << "\n"; //BuildMI(MBB, MI, Alpha::WTF, 0).addReg(SrcReg); if (EnableAlphaLSMark) @@ -92,7 +93,8 @@ AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB, void AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, - unsigned DestReg, int FrameIdx) const{ + unsigned DestReg, int FrameIdx, + const TargetRegisterClass *RC) const { //std::cerr << "Trying to load " << getPrettyName(DestReg) << " to " << FrameIdx << "\n"; if (EnableAlphaLSMark) BuildMI(MBB, MI, Alpha::MEMLABEL, 4).addImm(4).addImm(0).addImm(2) |
