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authorJakob Stoklund Olesen <stoklund@2pi.dk>2010-07-16 22:35:46 +0000
committerJakob Stoklund Olesen <stoklund@2pi.dk>2010-07-16 22:35:46 +0000
commit8289f785695aa15912dda5b3cd2251d9bbba3414 (patch)
treebdfb0a5157201555db524a4944cb7d328260f774 /llvm/lib/Target/Alpha/AlphaInstrInfo.cpp
parent8e767bde163c7ded5b4574439f254d28b5210383 (diff)
downloadbcm5719-llvm-8289f785695aa15912dda5b3cd2251d9bbba3414.tar.gz
bcm5719-llvm-8289f785695aa15912dda5b3cd2251d9bbba3414.zip
Remove the isMoveInstr() hook.
llvm-svn: 108567
Diffstat (limited to 'llvm/lib/Target/Alpha/AlphaInstrInfo.cpp')
-rw-r--r--llvm/lib/Target/Alpha/AlphaInstrInfo.cpp26
1 files changed, 0 insertions, 26 deletions
diff --git a/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp b/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp
index ad625a26941..5a2f5610fdb 100644
--- a/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp
+++ b/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp
@@ -27,32 +27,6 @@ AlphaInstrInfo::AlphaInstrInfo()
RI(*this) { }
-bool AlphaInstrInfo::isMoveInstr(const MachineInstr& MI,
- unsigned& sourceReg, unsigned& destReg,
- unsigned& SrcSR, unsigned& DstSR) const {
- unsigned oc = MI.getOpcode();
- if (oc == Alpha::BISr ||
- oc == Alpha::CPYSS ||
- oc == Alpha::CPYST ||
- oc == Alpha::CPYSSt ||
- oc == Alpha::CPYSTs) {
- // or r1, r2, r2
- // cpys(s|t) r1 r2 r2
- assert(MI.getNumOperands() >= 3 &&
- MI.getOperand(0).isReg() &&
- MI.getOperand(1).isReg() &&
- MI.getOperand(2).isReg() &&
- "invalid Alpha BIS instruction!");
- if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
- sourceReg = MI.getOperand(1).getReg();
- destReg = MI.getOperand(0).getReg();
- SrcSR = DstSR = 0;
- return true;
- }
- }
- return false;
-}
-
unsigned
AlphaInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const {
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