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authorJakob Stoklund Olesen <stoklund@2pi.dk>2010-07-10 22:43:03 +0000
committerJakob Stoklund Olesen <stoklund@2pi.dk>2010-07-10 22:43:03 +0000
commit60af0681cb02024e27ff65e30dc31414dab93aeb (patch)
treea1a1ab896a2972a642a7654b8f278cc2fbd2724c /llvm/lib/Target/Alpha/AlphaInstrInfo.cpp
parent0c76d6ec21a2ea55481300655bcf118c20795295 (diff)
downloadbcm5719-llvm-60af0681cb02024e27ff65e30dc31414dab93aeb.tar.gz
bcm5719-llvm-60af0681cb02024e27ff65e30dc31414dab93aeb.zip
Use COPY in targets
llvm-svn: 108063
Diffstat (limited to 'llvm/lib/Target/Alpha/AlphaInstrInfo.cpp')
-rw-r--r--llvm/lib/Target/Alpha/AlphaInstrInfo.cpp14
1 files changed, 4 insertions, 10 deletions
diff --git a/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp b/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp
index 22b72964c84..ab3097485a4 100644
--- a/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp
+++ b/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp
@@ -427,11 +427,8 @@ unsigned AlphaInstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
GlobalBaseReg = RegInfo.createVirtualRegister(&Alpha::GPRCRegClass);
- bool Ok = TII->copyRegToReg(FirstMBB, MBBI, GlobalBaseReg, Alpha::R29,
- &Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
- DebugLoc());
- assert(Ok && "Couldn't assign to global base register!");
- Ok = Ok; // Silence warning when assertions are turned off.
+ BuildMI(FirstMBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY),
+ GlobalBaseReg).addReg(Alpha::R29);
RegInfo.addLiveIn(Alpha::R29);
AlphaFI->setGlobalBaseReg(GlobalBaseReg);
@@ -455,11 +452,8 @@ unsigned AlphaInstrInfo::getGlobalRetAddr(MachineFunction *MF) const {
const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
GlobalRetAddr = RegInfo.createVirtualRegister(&Alpha::GPRCRegClass);
- bool Ok = TII->copyRegToReg(FirstMBB, MBBI, GlobalRetAddr, Alpha::R26,
- &Alpha::GPRCRegClass, &Alpha::GPRCRegClass,
- DebugLoc());
- assert(Ok && "Couldn't assign to global return address register!");
- Ok = Ok; // Silence warning when assertions are turned off.
+ BuildMI(FirstMBB, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY),
+ GlobalRetAddr).addReg(Alpha::R26);
RegInfo.addLiveIn(Alpha::R26);
AlphaFI->setGlobalRetAddr(GlobalRetAddr);
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