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authorAndrew Lenharth <andrewl@lenharth.org>2005-12-25 17:36:48 +0000
committerAndrew Lenharth <andrewl@lenharth.org>2005-12-25 17:36:48 +0000
commitf520093eb3f796e90e6a7ca01a50afe44bc09764 (patch)
tree53fa9dd49129546a5b2bfb830d2da39f7644e943 /llvm/lib/Target/Alpha/AlphaISelPattern.cpp
parent6b240e55d16557dd72767d9a5787d556f7b4c26c (diff)
downloadbcm5719-llvm-f520093eb3f796e90e6a7ca01a50afe44bc09764.tar.gz
bcm5719-llvm-f520093eb3f796e90e6a7ca01a50afe44bc09764.zip
add br pattern, unify JSR and BSR ISel instrs, and add BSR support for DAG
llvm-svn: 25011
Diffstat (limited to 'llvm/lib/Target/Alpha/AlphaISelPattern.cpp')
-rw-r--r--llvm/lib/Target/Alpha/AlphaISelPattern.cpp15
1 files changed, 8 insertions, 7 deletions
diff --git a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp
index afacf726cb3..92f16e8f7f3 100644
--- a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -824,17 +824,18 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
}
}
//build the right kind of call
- GlobalAddressSDNode *GASD = dyn_cast<GlobalAddressSDNode>(N.getOperand(1));
- if (GASD && !GASD->getGlobal()->isExternal()) {
+ if (N.getOperand(1).getOpcode() == AlphaISD::GPRelLo) {
//use PC relative branch call
AlphaLowering.restoreGP(BB);
- BuildMI(BB, Alpha::BSR, 1, Alpha::R26)
- .addGlobalAddress(GASD->getGlobal(),true);
+ BuildMI(BB, Alpha::BSR, 1)
+ .addGlobalAddress(cast<GlobalAddressSDNode>(N.getOperand(1)
+ .getOperand(0))
+ ->getGlobal(),true);
} else {
//no need to restore GP as we are doing an indirect call
Tmp1 = SelectExpr(N.getOperand(1));
BuildMI(BB, Alpha::BIS, 2, Alpha::R27).addReg(Tmp1).addReg(Tmp1);
- BuildMI(BB, Alpha::JSR, 2, Alpha::R26).addReg(Alpha::R27).addImm(0);
+ BuildMI(BB, Alpha::JSR, 0);
}
//push the result into a virtual register
@@ -1237,7 +1238,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) {
BuildMI(BB, Alpha::BIS, 2, Alpha::R24).addReg(Tmp2).addReg(Tmp2);
BuildMI(BB, Alpha::BIS, 2, Alpha::R25).addReg(Tmp3).addReg(Tmp3);
BuildMI(BB, Alpha::BIS, 2, Alpha::R27).addReg(Tmp1).addReg(Tmp1);
- BuildMI(BB, Alpha::JSRs, 2, Alpha::R23).addReg(Alpha::R27).addImm(0);
+ BuildMI(BB, Alpha::JSRs, 0);
BuildMI(BB, Alpha::BIS, 2, Result).addReg(Alpha::R27).addReg(Alpha::R27);
return Result;
@@ -1551,7 +1552,7 @@ void AlphaISel::Select(SDOperand N) {
cast<BasicBlockSDNode>(N.getOperand(1))->getBasicBlock();
Select(N.getOperand(0));
- BuildMI(BB, Alpha::BR, 1, Alpha::R31).addMBB(Dest);
+ BuildMI(BB, Alpha::BR, 1).addMBB(Dest);
return;
}
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