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authorAndrew Lenharth <andrewl@lenharth.org>2005-05-31 18:37:16 +0000
committerAndrew Lenharth <andrewl@lenharth.org>2005-05-31 18:37:16 +0000
commit676e4db6dc8068e71556326c7a98e0f36d77d7b8 (patch)
tree879dec1096a31c5fe72d194433afc72af6bfc153 /llvm/lib/Target/Alpha/AlphaISelPattern.cpp
parent973d85e660128624491479b7eabc266ff2ae7dc4 (diff)
downloadbcm5719-llvm-676e4db6dc8068e71556326c7a98e0f36d77d7b8.tar.gz
bcm5719-llvm-676e4db6dc8068e71556326c7a98e0f36d77d7b8.zip
switch to the new live in thing
llvm-svn: 22186
Diffstat (limited to 'llvm/lib/Target/Alpha/AlphaISelPattern.cpp')
-rw-r--r--llvm/lib/Target/Alpha/AlphaISelPattern.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp
index 59c59981f87..deed1905d60 100644
--- a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -212,8 +212,8 @@ AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
case MVT::i64:
args_int[count] = AddLiveIn(MF, args_int[count], getRegClassFor(VT));
argt = DAG.getCopyFromReg(args_int[count], VT, DAG.getRoot());
- // if (VT != MVT::i64)
- // argt = DAG.getNode(ISD::TRUNCATE, VT, argt);
+ if (VT != MVT::i64)
+ argt = DAG.getNode(ISD::TRUNCATE, VT, argt);
break;
}
DAG.setRoot(argt.getValue(1));
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