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| author | Andrew Lenharth <andrewl@lenharth.org> | 2005-07-04 20:07:21 +0000 |
|---|---|---|
| committer | Andrew Lenharth <andrewl@lenharth.org> | 2005-07-04 20:07:21 +0000 |
| commit | 26fa89e0a7791bd16ad33ef6a4836dacbff6b1ab (patch) | |
| tree | 68ba023007d56f949f3b928240d8e459344113de /llvm/lib/Target/Alpha/AlphaISelPattern.cpp | |
| parent | da852d51dff51f170dbd0088b2500a40126d7b57 (diff) | |
| download | bcm5719-llvm-26fa89e0a7791bd16ad33ef6a4836dacbff6b1ab.tar.gz bcm5719-llvm-26fa89e0a7791bd16ad33ef6a4836dacbff6b1ab.zip | |
check the correct VT
llvm-svn: 22332
Diffstat (limited to 'llvm/lib/Target/Alpha/AlphaISelPattern.cpp')
| -rw-r--r-- | llvm/lib/Target/Alpha/AlphaISelPattern.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp index ed285a3d9ff..bef529308e7 100644 --- a/llvm/lib/Target/Alpha/AlphaISelPattern.cpp +++ b/llvm/lib/Target/Alpha/AlphaISelPattern.cpp @@ -1642,7 +1642,7 @@ unsigned AlphaISel::SelectExpr(SDOperand N) { Select(Chain); unsigned r = dyn_cast<RegSDNode>(Node)->getReg(); //std::cerr << "CopyFromReg " << Result << " = " << r << "\n"; - if (isFP) + if (MVT::isFloatingPoint(N.getValue(0).getValueType())) BuildMI(BB, Alpha::CPYS, 2, Result).addReg(r).addReg(r); else BuildMI(BB, Alpha::BIS, 2, Result).addReg(r).addReg(r); |
