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| author | Anton Korobeynikov <asl@math.spbu.ru> | 2007-03-07 16:25:09 +0000 |
|---|---|---|
| committer | Anton Korobeynikov <asl@math.spbu.ru> | 2007-03-07 16:25:09 +0000 |
| commit | ed4b303c105000aa7be36645f7ff64bdca0e4c56 (patch) | |
| tree | 50356c9a3d06293d277bff579c6b730fda1ecd0b /llvm/lib/Target/Alpha/AlphaISelLowering.cpp | |
| parent | dd6ce6900ee666a4ab510b68be45aece4aecf6a5 (diff) | |
| download | bcm5719-llvm-ed4b303c105000aa7be36645f7ff64bdca0e4c56.tar.gz bcm5719-llvm-ed4b303c105000aa7be36645f7ff64bdca0e4c56.zip | |
Refactoring of formal parameter flags. Enable properly use of
zext/sext/aext stuff.
llvm-svn: 35008
Diffstat (limited to 'llvm/lib/Target/Alpha/AlphaISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/Alpha/AlphaISelLowering.cpp | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/llvm/lib/Target/Alpha/AlphaISelLowering.cpp b/llvm/lib/Target/Alpha/AlphaISelLowering.cpp index 1e7c79f9829..e8ae5a3e355 100644 --- a/llvm/lib/Target/Alpha/AlphaISelLowering.cpp +++ b/llvm/lib/Target/Alpha/AlphaISelLowering.cpp @@ -337,10 +337,12 @@ AlphaTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, case MVT::i32: // Promote the integer to 64 bits. If the input type is signed use a // sign extend, otherwise use a zero extend. - if (Args[i].isSigned) + if (Args[i].isSExt) Args[i].Node = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Args[i].Node); - else + else if (Args[i].isZExt) Args[i].Node = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64, Args[i].Node); + else + Args[i].Node = DAG.getNode(ISD::ANY_EXTEND, MVT::i64, Args[i].Node); break; case MVT::i64: case MVT::f64: |
