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| author | Andrew Lenharth <andrewl@lenharth.org> | 2006-06-13 18:27:39 +0000 |
|---|---|---|
| committer | Andrew Lenharth <andrewl@lenharth.org> | 2006-06-13 18:27:39 +0000 |
| commit | f570feeae31806c1d2a0c2641d821811453409d1 (patch) | |
| tree | 33d5963f3ce9fe05587726b33704885a4b09d962 /llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp | |
| parent | c5bb8ab1d559c83e67855047fc97eb360efdae2b (diff) | |
| download | bcm5719-llvm-f570feeae31806c1d2a0c2641d821811453409d1.tar.gz bcm5719-llvm-f570feeae31806c1d2a0c2641d821811453409d1.zip | |
It really helps to be returning to the correct place
llvm-svn: 28769
Diffstat (limited to 'llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp')
| -rw-r--r-- | llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp | 32 |
1 files changed, 5 insertions, 27 deletions
diff --git a/llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp index 0073beaa54c..885fcf445c2 100644 --- a/llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp +++ b/llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp @@ -124,7 +124,7 @@ namespace { private: SDOperand getGlobalBaseReg(); - SDOperand getRASaveReg(); + SDOperand getGlobalRetAddr(); SDOperand SelectCALL(SDOperand Op); }; @@ -141,7 +141,7 @@ SDOperand AlphaDAGToDAGISel::getGlobalBaseReg() { /// getRASaveReg - Grab the return address /// -SDOperand AlphaDAGToDAGISel::getRASaveReg() { +SDOperand AlphaDAGToDAGISel::getGlobalRetAddr() { return CurDAG->getCopyFromReg(CurDAG->getEntryNode(), AlphaLowering.getVRegRA(), MVT::i64); @@ -197,6 +197,9 @@ void AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { case AlphaISD::GlobalBaseReg: Result = getGlobalBaseReg(); return; + case AlphaISD::GlobalRetAddr: + Result = getGlobalRetAddr(); + return; case AlphaISD::DivCall: { SDOperand Chain = CurDAG->getEntryNode(); @@ -226,30 +229,6 @@ void AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { return; } - case ISD::RET: { - SDOperand Chain; - Select(Chain, N->getOperand(0)); // Token chain. - SDOperand InFlag(0,0); - - if (N->getNumOperands() == 3) { - SDOperand Val; - Select(Val, N->getOperand(1)); - if (N->getOperand(1).getValueType() == MVT::i64) { - Chain = CurDAG->getCopyToReg(Chain, Alpha::R0, Val, InFlag); - InFlag = Chain.getValue(1); - } else if (N->getOperand(1).getValueType() == MVT::f64 || - N->getOperand(1).getValueType() == MVT::f32) { - Chain = CurDAG->getCopyToReg(Chain, Alpha::F0, Val, InFlag); - InFlag = Chain.getValue(1); - } - } - Chain = CurDAG->getCopyToReg(Chain, Alpha::R26, getRASaveReg(), InFlag); - InFlag = Chain.getValue(1); - - // Finally, select this to a ret instruction. - Result = CurDAG->SelectNodeTo(N, Alpha::RETDAG, MVT::Other, Chain, InFlag); - return; - } case ISD::Constant: { uint64_t uval = cast<ConstantSDNode>(N)->getValue(); @@ -469,7 +448,6 @@ SDOperand AlphaDAGToDAGISel::SelectCALL(SDOperand Op) { assert(0 && "Unknown operand"); } - // Finally, once everything is in registers to pass to the call, emit the // call itself. if (Addr.getOpcode() == AlphaISD::GPRelLo) { |

