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author | Jim Lin <tclin914@gmail.com> | 2019-06-03 02:31:07 +0000 |
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committer | Jim Lin <tclin914@gmail.com> | 2019-06-03 02:31:07 +0000 |
commit | 20b14dacbbbf9fedc90c732b6dde9361b7b2283c (patch) | |
tree | 64a5859551d4c36c6b730669bcbdd262e6e49353 /llvm/lib/Target/AVR | |
parent | e71963c850d42f6d318af984d88afe859c2ba5ff (diff) | |
download | bcm5719-llvm-20b14dacbbbf9fedc90c732b6dde9361b7b2283c.tar.gz bcm5719-llvm-20b14dacbbbf9fedc90c732b6dde9361b7b2283c.zip |
[AVR] Fix incorrect source regclass of LDWRdPtr
Summary:
LDWRdPtr would be expanded to ld+ldd. ldd only accepts the pointer register is Y or Z.
So the register class of pointer of LDWRdPtr should be PTRDISPREGS instead of PTRREGS.
Reviewers: dylanmckay
Reviewed By: dylanmckay
Subscribers: dylanmckay, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62300
llvm-svn: 362351
Diffstat (limited to 'llvm/lib/Target/AVR')
-rw-r--r-- | llvm/lib/Target/AVR/AVRInstrInfo.td | 8 | ||||
-rw-r--r-- | llvm/lib/Target/AVR/AVRRegisterInfo.td | 4 |
2 files changed, 6 insertions, 6 deletions
diff --git a/llvm/lib/Target/AVR/AVRInstrInfo.td b/llvm/lib/Target/AVR/AVRInstrInfo.td index c458fe7de06..caca9b61760 100644 --- a/llvm/lib/Target/AVR/AVRInstrInfo.td +++ b/llvm/lib/Target/AVR/AVRInstrInfo.td @@ -1159,11 +1159,11 @@ isReMaterializable = 1 in // LDW Rd+1:Rd, P // // Expands to: - // ld Rd, P+ - // ld Rd+1, P + // ld Rd, P + // ldd Rd+1, P+1 let Constraints = "@earlyclobber $reg" in def LDWRdPtr : Pseudo<(outs DREGS:$reg), - (ins PTRREGS:$ptrreg), + (ins PTRDISPREGS:$ptrreg), "ldw\t$reg, $ptrreg", [(set i16:$reg, (load i16:$ptrreg))]>, Requires<[HasSRAM]>; @@ -1230,7 +1230,7 @@ isReMaterializable = 1 in // ldd Rd, P+q // ldd Rd+1, P+q+1 let Constraints = "@earlyclobber $dst" in - def LDDWRdPtrQ : Pseudo<(outs DREGS_WITHOUT_Z_WORKAROUND:$dst), + def LDDWRdPtrQ : Pseudo<(outs DREGS_WITHOUT_YZ_WORKAROUND:$dst), (ins memri:$memri), "lddw\t$dst, $memri", [(set i16:$dst, (load addr:$memri))]>, diff --git a/llvm/lib/Target/AVR/AVRRegisterInfo.td b/llvm/lib/Target/AVR/AVRRegisterInfo.td index e20f69beabe..ea38fedd22c 100644 --- a/llvm/lib/Target/AVR/AVRRegisterInfo.td +++ b/llvm/lib/Target/AVR/AVRRegisterInfo.td @@ -165,14 +165,14 @@ def DREGS : RegisterClass<"AVR", [i16], 8, // cannot use Z; it's simply a workaround a regalloc bug. // // More information can be found in PR39553. -def DREGS_WITHOUT_Z_WORKAROUND : RegisterClass<"AVR", [i16], 8, +def DREGS_WITHOUT_YZ_WORKAROUND : RegisterClass<"AVR", [i16], 8, ( // Return value and arguments. add R25R24, R19R18, R21R20, R23R22, // Scratch registers. R27R26, // Callee saved registers. - R29R28, R17R16, R15R14, R13R12, R11R10, + R17R16, R15R14, R13R12, R11R10, R9R8, R7R6, R5R4, R3R2, R1R0 )>; |