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| author | Dylan McKay <me@dylanmckay.io> | 2019-06-01 12:38:56 +0000 |
|---|---|---|
| committer | Dylan McKay <me@dylanmckay.io> | 2019-06-01 12:38:56 +0000 |
| commit | 45eb4c7e55341c0b83a21dedecc092e273795eda (patch) | |
| tree | b6e59c937d1726830092715a268f93b2783581f6 /llvm/lib/Target/AVR/AVRRegisterInfo.cpp | |
| parent | e6d1a80370f2e465c5aa61f6ba5f16de513aa393 (diff) | |
| download | bcm5719-llvm-45eb4c7e55341c0b83a21dedecc092e273795eda.tar.gz bcm5719-llvm-45eb4c7e55341c0b83a21dedecc092e273795eda.zip | |
[AVR] Disable register coalescing to the PTRDISPREGS class
If we would allow register coalescing on PTRDISPREGS class then register
allocator can lock Z register to some virtual register. Larger instructions
requiring a memory acces then fail during the register allocation phase since
there is no available register to hold a pointer if Y register was already
taken for a stack frame. This patch prevents it by keeping Z register
spillable. It does it by not allowing coalescer to lock it.
Original discussion on https://github.com/avr-rust/rust/issues/128.
llvm-svn: 362298
Diffstat (limited to 'llvm/lib/Target/AVR/AVRRegisterInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/AVR/AVRRegisterInfo.cpp | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/llvm/lib/Target/AVR/AVRRegisterInfo.cpp b/llvm/lib/Target/AVR/AVRRegisterInfo.cpp index 8dc31fe066b..0aae34d7dfd 100644 --- a/llvm/lib/Target/AVR/AVRRegisterInfo.cpp +++ b/llvm/lib/Target/AVR/AVRRegisterInfo.cpp @@ -16,6 +16,7 @@ #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/IR/Function.h" #include "llvm/CodeGen/TargetFrameLowering.h" @@ -272,4 +273,18 @@ void AVRRegisterInfo::splitReg(unsigned Reg, HiReg = getSubReg(Reg, AVR::sub_hi); } +bool AVRRegisterInfo::shouldCoalesce(MachineInstr *MI, + const TargetRegisterClass *SrcRC, + unsigned SubReg, + const TargetRegisterClass *DstRC, + unsigned DstSubReg, + const TargetRegisterClass *NewRC, + LiveIntervals &LIS) const { + if(this->getRegClass(AVR::PTRDISPREGSRegClassID)->hasSubClassEq(NewRC)) { + return false; + } + + return TargetRegisterInfo::shouldCoalesce(MI, SrcRC, SubReg, DstRC, DstSubReg, NewRC, LIS); +} + } // end of namespace llvm |

