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| author | Bradley Smith <bradley.smith@arm.com> | 2014-04-09 14:44:44 +0000 |
|---|---|---|
| committer | Bradley Smith <bradley.smith@arm.com> | 2014-04-09 14:44:44 +0000 |
| commit | a2308f47d3415e0d0bcb4ae2a1f0b36615ed010c (patch) | |
| tree | 1a8468f29ca45837b50d8b190f8f907edd901a0f /llvm/lib/Target/ARM64/Disassembler | |
| parent | f280e91849daf64ae8fa3a946e46224dca98c39a (diff) | |
| download | bcm5719-llvm-a2308f47d3415e0d0bcb4ae2a1f0b36615ed010c.tar.gz bcm5719-llvm-a2308f47d3415e0d0bcb4ae2a1f0b36615ed010c.zip | |
[ARM64] Flag setting logical/add/sub immediate instructions don't use SP.
llvm-svn: 205895
Diffstat (limited to 'llvm/lib/Target/ARM64/Disassembler')
| -rw-r--r-- | llvm/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp | 18 |
1 files changed, 14 insertions, 4 deletions
diff --git a/llvm/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp b/llvm/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp index 294962c5f35..8f9b79c90a8 100644 --- a/llvm/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp +++ b/llvm/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp @@ -1417,13 +1417,17 @@ static DecodeStatus DecodeAddSubERegInstruction(llvm::MCInst &Inst, DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder); break; case ARM64::ADDXrx64: - case ARM64::ADDSXrx64: case ARM64::SUBXrx64: - case ARM64::SUBSXrx64: DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); break; + case ARM64::SUBSXrx64: + case ARM64::ADDSXrx64: + DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); + DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder); + DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder); + break; } Inst.addOperand(MCOperand::CreateImm(extend)); @@ -1439,13 +1443,19 @@ static DecodeStatus DecodeLogicalImmInstruction(llvm::MCInst &Inst, unsigned imm; if (Datasize) { - DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); + if (Inst.getOpcode() == ARM64::ANDSXri) + DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder); + else + DecodeGPR64spRegisterClass(Inst, Rd, Addr, Decoder); DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder); imm = fieldFromInstruction(insn, 10, 13); if (!ARM64_AM::isValidDecodeLogicalImmediate(imm, 64)) return Fail; } else { - DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); + if (Inst.getOpcode() == ARM64::ANDSWri) + DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder); + else + DecodeGPR32spRegisterClass(Inst, Rd, Addr, Decoder); DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder); imm = fieldFromInstruction(insn, 10, 12); if (!ARM64_AM::isValidDecodeLogicalImmediate(imm, 32)) |
