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authorBradley Smith <bradley.smith@arm.com>2014-04-09 14:41:45 +0000
committerBradley Smith <bradley.smith@arm.com>2014-04-09 14:41:45 +0000
commit87c60e00d5f9bca42413f660966b8679634321ae (patch)
tree79dd56cc06791aab7fa7d504f18043adabeb627c /llvm/lib/Target/ARM64/Disassembler
parentcd91e5cd0c1f3076f76cfc1abf356a6dc15a2575 (diff)
downloadbcm5719-llvm-87c60e00d5f9bca42413f660966b8679634321ae.tar.gz
bcm5719-llvm-87c60e00d5f9bca42413f660966b8679634321ae.zip
[ARM64] MOVK with sf=0 and hw<1>=1 is unallocated. Shift amount for ADD/SUB instructions is unallocated if shift > 4.
llvm-svn: 205859
Diffstat (limited to 'llvm/lib/Target/ARM64/Disassembler')
-rw-r--r--llvm/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp6
1 files changed, 6 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp b/llvm/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
index b522939af8a..55267b06409 100644
--- a/llvm/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
+++ b/llvm/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
@@ -906,6 +906,8 @@ static DecodeStatus DecodeMoveImmInstruction(llvm::MCInst &Inst, uint32_t insn,
case ARM64::MOVZWi:
case ARM64::MOVNWi:
case ARM64::MOVKWi:
+ if (shift & (1U << 5))
+ return Fail;
DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
break;
case ARM64::MOVZXi:
@@ -1339,6 +1341,10 @@ static DecodeStatus DecodeAddSubERegInstruction(llvm::MCInst &Inst,
unsigned Rm = fieldFromInstruction(insn, 16, 5);
unsigned extend = fieldFromInstruction(insn, 10, 6);
+ unsigned shift = extend & 0x7;
+ if (shift > 4)
+ return Fail;
+
switch (Inst.getOpcode()) {
default:
return Fail;
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