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authorBradley Smith <bradley.smith@arm.com>2014-05-12 11:49:16 +0000
committerBradley Smith <bradley.smith@arm.com>2014-05-12 11:49:16 +0000
commitbbec45a4f1cf23c2d064bb92cd3f0b3596c41a4c (patch)
tree15de5432e3aa436758c4304f280e527e3f252135 /llvm/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
parentfb4333b093352de9298fff0f5307d60953a3520b (diff)
downloadbcm5719-llvm-bbec45a4f1cf23c2d064bb92cd3f0b3596c41a4c.tar.gz
bcm5719-llvm-bbec45a4f1cf23c2d064bb92cd3f0b3596c41a4c.zip
[ARM64] Add proper bounds checking/diagnostics to logical shifts
llvm-svn: 208540
Diffstat (limited to 'llvm/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp')
-rw-r--r--llvm/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp29
1 files changed, 17 insertions, 12 deletions
diff --git a/llvm/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp b/llvm/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
index b2583a0f124..760c2fcb59c 100644
--- a/llvm/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
+++ b/llvm/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
@@ -845,6 +845,18 @@ public:
ST == ARM64_AM::ASR) && ARM64_AM::getShiftValue(Shifter.Val) < width;
}
+ template <unsigned width>
+ bool isLogicalShifter() const {
+ if (!isShifter())
+ return false;
+
+ // A logical shifter is LSL, LSR, ASR or ROR.
+ ARM64_AM::ShiftType ST = ARM64_AM::getShiftType(Shifter.Val);
+ return (ST == ARM64_AM::LSL || ST == ARM64_AM::LSR ||
+ ST == ARM64_AM::ASR || ST == ARM64_AM::ROR) &&
+ ARM64_AM::getShiftValue(Shifter.Val) < width;
+ }
+
bool isMovImm32Shifter() const {
if (!isShifter())
return false;
@@ -1453,6 +1465,11 @@ public:
Inst.addOperand(MCOperand::CreateImm(getShifter()));
}
+ void addLogicalShifterOperands(MCInst &Inst, unsigned N) const {
+ assert(N == 1 && "Invalid number of operands!");
+ Inst.addOperand(MCOperand::CreateImm(getShifter()));
+ }
+
void addMovImm32ShifterOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
Inst.addOperand(MCOperand::CreateImm(getShifter()));
@@ -3677,18 +3694,6 @@ bool ARM64AsmParser::validateInstruction(MCInst &Inst,
// in the instructions being checked and this keeps the nested conditionals
// to a minimum.
switch (Inst.getOpcode()) {
- case ARM64::ANDWrs:
- case ARM64::ANDSWrs:
- case ARM64::EORWrs:
- case ARM64::ORRWrs: {
- if (!Inst.getOperand(3).isImm())
- return Error(Loc[3], "immediate value expected");
- int64_t shifter = Inst.getOperand(3).getImm();
- ARM64_AM::ShiftType ST = ARM64_AM::getShiftType(shifter);
- if (ST == ARM64_AM::LSL && shifter > 31)
- return Error(Loc[3], "shift value out of range");
- return false;
- }
case ARM64::ADDSWri:
case ARM64::ADDSXri:
case ARM64::ADDWri:
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