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authorJim Grosbach <grosbach@apple.com>2014-04-21 21:45:57 +0000
committerJim Grosbach <grosbach@apple.com>2014-04-21 21:45:57 +0000
commit9515c52294c650755f8056a5ee77e32c08c97833 (patch)
treecdab1c51314a08ce0ea9884ecbdcb5a30e8f949a /llvm/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
parentac901086e509c91d9b45627850b1910f5d39553c (diff)
downloadbcm5719-llvm-9515c52294c650755f8056a5ee77e32c08c97833.tar.gz
bcm5719-llvm-9515c52294c650755f8056a5ee77e32c08c97833.zip
ARM64: Improve diagnostics for malformed reg+reg addressing mode.
Make sure only general purpose registers are valid for offset regs and that 32-bit regs are only valid for sxtw and uxtw extends. llvm-svn: 206799
Diffstat (limited to 'llvm/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp')
-rw-r--r--llvm/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp13
1 files changed, 12 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp b/llvm/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
index 24ed77a020f..4648f5cb0f8 100644
--- a/llvm/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
+++ b/llvm/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
@@ -1416,7 +1416,7 @@ public:
assert(N == 3 && "Invalid number of operands!");
Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
- Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
+ Inst.addOperand(MCOperand::CreateReg(getXRegFromWReg(Mem.OffsetRegNum)));
unsigned ExtendImm = ARM64_AM::getMemExtendImm(Mem.ExtType, DoShift);
Inst.addOperand(MCOperand::CreateImm(ExtendImm));
}
@@ -2894,6 +2894,17 @@ bool ARM64AsmParser::parseMemory(OperandVector &Operands) {
Parser.Lex(); // Eat the extend op.
+ // A 32-bit offset register is only valid for [SU]/XTW extend
+ // operators.
+ if (isGPR32Register(Reg2)) {
+ if (ExtOp != ARM64_AM::UXTW &&
+ ExtOp != ARM64_AM::SXTW)
+ return Error(ExtLoc, "32-bit general purpose offset register "
+ "requires sxtw or uxtw extend");
+ } else if (!isGPR64Register(Reg2))
+ return Error(OffsetLoc,
+ "64-bit general purpose offset register expected");
+
bool Hash = getLexer().is(AsmToken::Hash);
if (getLexer().is(AsmToken::RBrac)) {
// No immediate operand.
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