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| author | Tim Northover <tnorthover@apple.com> | 2014-05-08 10:30:56 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2014-05-08 10:30:56 +0000 |
| commit | 18f8bb84faa1d6cb44e1ca29e783dfd309f109df (patch) | |
| tree | 3c1bbeb6e190eb7a7136e246dd1bb63f82ca3bf4 /llvm/lib/Target/ARM64/ARM64FastISel.cpp | |
| parent | 9661ec0ec398a3526ce95e94b98e2adb49e68f8b (diff) | |
| download | bcm5719-llvm-18f8bb84faa1d6cb44e1ca29e783dfd309f109df.tar.gz bcm5719-llvm-18f8bb84faa1d6cb44e1ca29e783dfd309f109df.zip | |
ARM64: make sure FastISel emits SSA MachineInstrs
We need to use a temporary register for a 2-step operation like REM.
llvm-svn: 208297
Diffstat (limited to 'llvm/lib/Target/ARM64/ARM64FastISel.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM64/ARM64FastISel.cpp | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/llvm/lib/Target/ARM64/ARM64FastISel.cpp b/llvm/lib/Target/ARM64/ARM64FastISel.cpp index 78cde1c22c9..0d4001ebf67 100644 --- a/llvm/lib/Target/ARM64/ARM64FastISel.cpp +++ b/llvm/lib/Target/ARM64/ARM64FastISel.cpp @@ -1849,14 +1849,15 @@ bool ARM64FastISel::SelectRem(const Instruction *I, unsigned ISDOpcode) { if (!Src1Reg) return false; - unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT)); - BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(DivOpc), ResultReg) + unsigned QuotReg = createResultReg(TLI.getRegClassFor(DestVT)); + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(DivOpc), QuotReg) .addReg(Src0Reg) .addReg(Src1Reg); // The remainder is computed as numerator - (quotient * denominator) using the // MSUB instruction. + unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT)); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MSubOpc), ResultReg) - .addReg(ResultReg) + .addReg(QuotReg) .addReg(Src1Reg) .addReg(Src0Reg); UpdateValueMap(I, ResultReg); |
