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| author | Tim Northover <tnorthover@apple.com> | 2014-05-02 14:54:15 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2014-05-02 14:54:15 +0000 |
| commit | d0b07e133b1663ed174ace67694312429b855d88 (patch) | |
| tree | c6eb2f8805cb9c44a183c9e182ea0ac5823166c9 /llvm/lib/Target/ARM64/ARM64AsmPrinter.cpp | |
| parent | a82eaa70f17a247f6b16c31f0c13406a105ceee8 (diff) | |
| download | bcm5719-llvm-d0b07e133b1663ed174ace67694312429b855d88.tar.gz bcm5719-llvm-d0b07e133b1663ed174ace67694312429b855d88.zip | |
AArch64/ARM64: support indexed loads/stores on vector types.
While post-indexed LD1/ST1 instructions do exist for vector loads,
this patch makes use of the more flexible addressing-modes in LDR/STR
instructions.
llvm-svn: 207838
Diffstat (limited to 'llvm/lib/Target/ARM64/ARM64AsmPrinter.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM64/ARM64AsmPrinter.cpp | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM64/ARM64AsmPrinter.cpp b/llvm/lib/Target/ARM64/ARM64AsmPrinter.cpp index bc6fef1aa43..5531101fe2f 100644 --- a/llvm/lib/Target/ARM64/ARM64AsmPrinter.cpp +++ b/llvm/lib/Target/ARM64/ARM64AsmPrinter.cpp @@ -427,6 +427,7 @@ static unsigned getRealIndexedOpcode(unsigned Opc) { switch (Opc) { case ARM64::LDRXpre_isel: return ARM64::LDRXpre; case ARM64::LDRWpre_isel: return ARM64::LDRWpre; + case ARM64::LDRQpre_isel: return ARM64::LDRQpre; case ARM64::LDRDpre_isel: return ARM64::LDRDpre; case ARM64::LDRSpre_isel: return ARM64::LDRSpre; case ARM64::LDRBBpre_isel: return ARM64::LDRBBpre; @@ -437,6 +438,7 @@ static unsigned getRealIndexedOpcode(unsigned Opc) { case ARM64::LDRSHXpre_isel: return ARM64::LDRSHXpre; case ARM64::LDRSWpre_isel: return ARM64::LDRSWpre; + case ARM64::LDRQpost_isel: return ARM64::LDRQpost; case ARM64::LDRDpost_isel: return ARM64::LDRDpost; case ARM64::LDRSpost_isel: return ARM64::LDRSpost; case ARM64::LDRXpost_isel: return ARM64::LDRXpost; @@ -453,6 +455,7 @@ static unsigned getRealIndexedOpcode(unsigned Opc) { case ARM64::STRWpre_isel: return ARM64::STRWpre; case ARM64::STRHHpre_isel: return ARM64::STRHHpre; case ARM64::STRBBpre_isel: return ARM64::STRBBpre; + case ARM64::STRQpre_isel: return ARM64::STRQpre; case ARM64::STRDpre_isel: return ARM64::STRDpre; case ARM64::STRSpre_isel: return ARM64::STRSpre; } @@ -494,6 +497,7 @@ void ARM64AsmPrinter::EmitInstruction(const MachineInstr *MI) { case ARM64::LDRBBpre_isel: case ARM64::LDRXpre_isel: case ARM64::LDRWpre_isel: + case ARM64::LDRQpre_isel: case ARM64::LDRDpre_isel: case ARM64::LDRSpre_isel: case ARM64::LDRSBWpre_isel: @@ -501,6 +505,7 @@ void ARM64AsmPrinter::EmitInstruction(const MachineInstr *MI) { case ARM64::LDRSHWpre_isel: case ARM64::LDRSHXpre_isel: case ARM64::LDRSWpre_isel: + case ARM64::LDRQpost_isel: case ARM64::LDRDpost_isel: case ARM64::LDRSpost_isel: case ARM64::LDRXpost_isel: @@ -525,6 +530,7 @@ void ARM64AsmPrinter::EmitInstruction(const MachineInstr *MI) { case ARM64::STRWpre_isel: case ARM64::STRHHpre_isel: case ARM64::STRBBpre_isel: + case ARM64::STRQpre_isel: case ARM64::STRDpre_isel: case ARM64::STRSpre_isel: { MCInst TmpInst; |
