[ARM] Tidy-up condition-code support functions

Move condition code support functions to Utils and remove code duplication.

Reviewed by: @fhahn, @asb
Differential Revision: https://reviews.llvm.org/D37179

llvm-svn: 311860

1 files changed, 86 insertions, 0 deletions

diff --git a/llvm/lib/Target/ARM/Utils/ARMBaseInfo.h b/llvm/lib/Target/ARM/Utils/ARMBaseInfo.h
index 56abd8ba86b..f32d8223f53 100644
--- a/llvm/lib/Target/ARM/Utils/ARMBaseInfo.h
+++ b/llvm/lib/Target/ARM/Utils/ARMBaseInfo.h
@@ -24,6 +24,92 @@
 
 namespace llvm {
 
+// Enums corresponding to ARM condition codes
+namespace ARMCC {
+// The CondCodes constants map directly to the 4-bit encoding of the
+// condition field for predicated instructions.
+enum CondCodes { // Meaning (integer)          Meaning (floating-point)
+  EQ,            // Equal                      Equal
+  NE,            // Not equal                  Not equal, or unordered
+  HS,            // Carry set                  >, ==, or unordered
+  LO,            // Carry clear                Less than
+  MI,            // Minus, negative            Less than
+  PL,            // Plus, positive or zero     >, ==, or unordered
+  VS,            // Overflow                   Unordered
+  VC,            // No overflow                Not unordered
+  HI,            // Unsigned higher            Greater than, or unordered
+  LS,            // Unsigned lower or same     Less than or equal
+  GE,            // Greater than or equal      Greater than or equal
+  LT,            // Less than                  Less than, or unordered
+  GT,            // Greater than               Greater than
+  LE,            // Less than or equal         <, ==, or unordered
+  AL             // Always (unconditional)     Always (unconditional)
+};
+
+inline static CondCodes getOppositeCondition(CondCodes CC) {
+  switch (CC) {
+  default: llvm_unreachable("Unknown condition code");
+  case EQ: return NE;
+  case NE: return EQ;
+  case HS: return LO;
+  case LO: return HS;
+  case MI: return PL;
+  case PL: return MI;
+  case VS: return VC;
+  case VC: return VS;
+  case HI: return LS;
+  case LS: return HI;
+  case GE: return LT;
+  case LT: return GE;
+  case GT: return LE;
+  case LE: return GT;
+  }
+}
+} // end namespace ARMCC
+
+inline static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
+  switch (CC) {
+  case ARMCC::EQ:  return "eq";
+  case ARMCC::NE:  return "ne";
+  case ARMCC::HS:  return "hs";
+  case ARMCC::LO:  return "lo";
+  case ARMCC::MI:  return "mi";
+  case ARMCC::PL:  return "pl";
+  case ARMCC::VS:  return "vs";
+  case ARMCC::VC:  return "vc";
+  case ARMCC::HI:  return "hi";
+  case ARMCC::LS:  return "ls";
+  case ARMCC::GE:  return "ge";
+  case ARMCC::LT:  return "lt";
+  case ARMCC::GT:  return "gt";
+  case ARMCC::LE:  return "le";
+  case ARMCC::AL:  return "al";
+  }
+  llvm_unreachable("Unknown condition code");
+}
+
+inline static unsigned ARMCondCodeFromString(StringRef CC) {
+  return StringSwitch<unsigned>(CC.lower())
+    .Case("eq", ARMCC::EQ)
+    .Case("ne", ARMCC::NE)
+    .Case("hs", ARMCC::HS)
+    .Case("cs", ARMCC::HS)
+    .Case("lo", ARMCC::LO)
+    .Case("cc", ARMCC::LO)
+    .Case("mi", ARMCC::MI)
+    .Case("pl", ARMCC::PL)
+    .Case("vs", ARMCC::VS)
+    .Case("vc", ARMCC::VC)
+    .Case("hi", ARMCC::HI)
+    .Case("ls", ARMCC::LS)
+    .Case("ge", ARMCC::GE)
+    .Case("lt", ARMCC::LT)
+    .Case("gt", ARMCC::GT)
+    .Case("le", ARMCC::LE)
+    .Case("al", ARMCC::AL)
+    .Default(~0U);
+}
+
 // System Registers
 namespace ARMSysReg {
   struct MClassSysReg {