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authorSimon Tatham <simon.tatham@arm.com>2019-06-28 09:28:39 +0000
committerSimon Tatham <simon.tatham@arm.com>2019-06-28 09:28:39 +0000
commit29ff1b4f4653f2c77501ca4e1014c710e602aa08 (patch)
tree37ee4ac17ed5e1677c409988f8300009ab41f724 /llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
parente662b6985a8af483a4e7c541f8b67628452d147f (diff)
downloadbcm5719-llvm-29ff1b4f4653f2c77501ca4e1014c710e602aa08.tar.gz
bcm5719-llvm-29ff1b4f4653f2c77501ca4e1014c710e602aa08.zip
[ARM] Fix integer UB in MVE load/store immediate handling.
llvm-svn: 364635
Diffstat (limited to 'llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp')
-rw-r--r--llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp11
1 files changed, 7 insertions, 4 deletions
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
index c506f267731..dca6fe37d49 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp
@@ -1621,12 +1621,15 @@ getT2AddrModeImmOpValue(const MCInst &MI, unsigned OpNum,
// If the immediate is B bits long, we need B+1 bits in order
// to represent the (inverse of the) sign bit.
Value <<= (Bits + 1);
- int32_t tmp = (int32_t)MO2.getImm() >> Shift;
- if (tmp < 0)
+ int32_t tmp = (int32_t)MO2.getImm();
+ if (tmp == INT32_MIN) { // represents subtracting zero rather than adding it
+ tmp = 0;
+ } else if (tmp < 0) {
tmp = abs(tmp);
- else
+ } else {
Value |= (1U << Bits); // Set the ADD bit
- Value |= tmp & ((1U << Bits) - 1);
+ }
+ Value |= (tmp >> Shift) & ((1U << Bits) - 1);
return Value;
}
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