diff options
| author | Logan Chien <tzuhsiang.chien@gmail.com> | 2012-12-12 07:14:46 +0000 |
|---|---|---|
| committer | Logan Chien <tzuhsiang.chien@gmail.com> | 2012-12-12 07:14:46 +0000 |
| commit | 4dd14fb5eb6cd5d8ac822e7d37b6c3ca0475e762 (patch) | |
| tree | b12b4b6a70b2f8b8f20363b78723eee125bc1e83 /llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp | |
| parent | ad80c5ef76398415b6d7f1db4a35cf73103ebbf1 (diff) | |
| download | bcm5719-llvm-4dd14fb5eb6cd5d8ac822e7d37b6c3ca0475e762.tar.gz bcm5719-llvm-4dd14fb5eb6cd5d8ac822e7d37b6c3ca0475e762.zip | |
Add ARM NONE and PREL31 relocation types.
Add R_ARM_NONE and R_ARM_PREL31 relocation types
to MCExpr. Both of them will be used while
generating .ARM.extab and .ARM.exidx sections.
llvm-svn: 169965
Diffstat (limited to 'llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp index 813c7844ec5..9193e40bedf 100644 --- a/llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp +++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp @@ -133,6 +133,7 @@ const MCSymbol *ARMELFObjectWriter::ExplicitRelSym(const MCAssembler &Asm, switch (RelocType) { default: EmitThisSym = true; break; case ELF::R_ARM_ABS32: EmitThisSym = false; break; + case ELF::R_ARM_PREL31: EmitThisSym = false; break; } } @@ -225,6 +226,9 @@ unsigned ARMELFObjectWriter::GetRelocTypeInner(const MCValue &Target, case FK_Data_4: switch (Modifier) { default: llvm_unreachable("Unsupported Modifier"); + case MCSymbolRefExpr::VK_ARM_NONE: + Type = ELF::R_ARM_NONE; + break; case MCSymbolRefExpr::VK_ARM_GOT: Type = ELF::R_ARM_GOT_BREL; break; @@ -249,7 +253,10 @@ unsigned ARMELFObjectWriter::GetRelocTypeInner(const MCValue &Target, case MCSymbolRefExpr::VK_ARM_TARGET2: Type = ELF::R_ARM_TARGET2; break; - } + case MCSymbolRefExpr::VK_ARM_PREL31: + Type = ELF::R_ARM_PREL31; + break; + } break; case ARM::fixup_arm_ldst_pcrel_12: case ARM::fixup_arm_pcrel_10: |
