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authorReid Kleckner <rnk@google.com>2015-12-16 19:21:03 +0000
committerReid Kleckner <rnk@google.com>2015-12-16 19:21:03 +0000
commit187d33ee74d26da242b48f36fee6909cd6f8db40 (patch)
tree5821bdbd8735cbdfe7f2d1a75cbdba88fdad0564 /llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h
parent3e8f56565d895999ae9f7b9ad5b0a45c55e60aba (diff)
downloadbcm5719-llvm-187d33ee74d26da242b48f36fee6909cd6f8db40.tar.gz
bcm5719-llvm-187d33ee74d26da242b48f36fee6909cd6f8db40.zip
Revert "[ARM] Add ARMv8.2-A FP16 scalar instructions"
This reverts commit r255762. llvm-svn: 255806
Diffstat (limited to 'llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h')
-rw-r--r--llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h51
1 files changed, 1 insertions, 50 deletions
diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h
index 3959eab966a..b03cada9a64 100644
--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h
+++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h
@@ -486,7 +486,7 @@ namespace ARM_AM {
// addrmode5 := reg +/- imm8*4
//
// The first operand is always a Reg. The second operand encodes the
- // operation (add or subtract) in bit 8 and the immediate in bits 0-7.
+ // operation in bit 8 and the immediate in bits 0-7.
/// getAM5Opc - This function encodes the addrmode5 opc field.
static inline unsigned getAM5Opc(AddrOpc Opc, unsigned char Offset) {
@@ -501,29 +501,6 @@ namespace ARM_AM {
}
//===--------------------------------------------------------------------===//
- // Addressing Mode #5 FP16
- //===--------------------------------------------------------------------===//
- //
- // This is used for coprocessor instructions, such as 16-bit FP load/stores.
- //
- // addrmode5fp16 := reg +/- imm8*2
- //
- // The first operand is always a Reg. The second operand encodes the
- // operation (add or subtract) in bit 8 and the immediate in bits 0-7.
-
- /// getAM5FP16Opc - This function encodes the addrmode5fp16 opc field.
- static inline unsigned getAM5FP16Opc(AddrOpc Opc, unsigned char Offset) {
- bool isSub = Opc == sub;
- return ((int)isSub << 8) | Offset;
- }
- static inline unsigned char getAM5FP16Offset(unsigned AM5Opc) {
- return AM5Opc & 0xFF;
- }
- static inline AddrOpc getAM5FP16Op(unsigned AM5Opc) {
- return ((AM5Opc >> 8) & 1) ? sub : add;
- }
-
- //===--------------------------------------------------------------------===//
// Addressing Mode #6
//===--------------------------------------------------------------------===//
//
@@ -673,32 +650,6 @@ namespace ARM_AM {
return FPUnion.F;
}
- /// getFP16Imm - Return an 8-bit floating-point version of the 16-bit
- /// floating-point value. If the value cannot be represented as an 8-bit
- /// floating-point value, then return -1.
- static inline int getFP16Imm(const APInt &Imm) {
- uint32_t Sign = Imm.lshr(15).getZExtValue() & 1;
- int32_t Exp = (Imm.lshr(10).getSExtValue() & 0x1f) - 15; // -14 to 15
- int64_t Mantissa = Imm.getZExtValue() & 0x3ff; // 10 bits
-
- // We can handle 4 bits of mantissa.
- // mantissa = (16+UInt(e:f:g:h))/16.
- if (Mantissa & 0x3f)
- return -1;
- Mantissa >>= 6;
-
- // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
- if (Exp < -3 || Exp > 4)
- return -1;
- Exp = ((Exp+3) & 0x7) ^ 4;
-
- return ((int)Sign << 7) | (Exp << 4) | Mantissa;
- }
-
- static inline int getFP16Imm(const APFloat &FPImm) {
- return getFP16Imm(FPImm.bitcastToAPInt());
- }
-
/// getFP32Imm - Return an 8-bit floating-point version of the 32-bit
/// floating-point value. If the value cannot be represented as an 8-bit
/// floating-point value, then return -1.
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