[ARM] Rename MVE instructions in Tablegen for consistency.

Summary:
Their names began with a mishmash of `MVE_`, `t2` and no prefix at
all. Now they all start with `MVE_`, which seems like a reasonable
choice on the grounds that (a) NEON is the thing they're most at risk
of being confused with, and (b) MVE implies Thumb-2, so a prefix
indicating MVE is strictly more specific than one indicating Thumb-2.

Reviewers: ostannard, SjoerdMeijer, dmgreen

Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63492

llvm-svn: 363690

1 files changed, 6 insertions, 6 deletions

diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index b5cc967d51a..304f648d2a6 100644
--- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -6042,13 +6042,13 @@ static DecodeStatus DecodeMVEOverlappingLongShift(
     unsigned Rda = fieldFromInstruction(Insn, 16, 4);
 
     switch (Inst.getOpcode()) {
-      case ARM::t2ASRLr:
-      case ARM::t2SQRSHRL:
-        Inst.setOpcode(ARM::t2SQRSHR);
+      case ARM::MVE_ASRLr:
+      case ARM::MVE_SQRSHRL:
+        Inst.setOpcode(ARM::MVE_SQRSHR);
         break;
-      case ARM::t2LSLLr:
-      case ARM::t2UQRSHLL:
-        Inst.setOpcode(ARM::t2UQRSHL);
+      case ARM::MVE_LSLLr:
+      case ARM::MVE_UQRSHLL:
+        Inst.setOpcode(ARM::MVE_UQRSHL);
         break;
       default:
         llvm_unreachable("Unexpected starting opcode!");