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| author | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2019-06-20 14:59:28 +0000 |
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| committer | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2019-06-20 14:59:28 +0000 |
| commit | 082ffa9960cc14e76313e29caba011ef5552f0a6 (patch) | |
| tree | d5712d5cb1c724c381662e6f45be586b346f5bb8 /llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp | |
| parent | 30ea0c4d74e7c363ef0fc14f1c9a28d0ed657368 (diff) | |
| download | bcm5719-llvm-082ffa9960cc14e76313e29caba011ef5552f0a6.tar.gz bcm5719-llvm-082ffa9960cc14e76313e29caba011ef5552f0a6.zip | |
Virtualize TargetInstrInfo::getRegClass()
AMDGPU target needs to override getRegClass() used during
instruction selection. We now may have either 32 or 64 bit
conditional registers used in the same instructions. For
that purpose special SReg_1 register class is created which
is dynamically resolved to either SReg_64 or SGPR_32 depending
on the subtarget attributes.
Differential Revision: https://reviews.llvm.org/D63205
llvm-svn: 363931
Diffstat (limited to 'llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions
