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| author | John Brawn <john.brawn@arm.com> | 2017-03-07 14:42:03 +0000 |
|---|---|---|
| committer | John Brawn <john.brawn@arm.com> | 2017-03-07 14:42:03 +0000 |
| commit | eba9fdac7e131c6c99824cfd763989cc74965007 (patch) | |
| tree | 1b49e341faeea0fa700d3ba1896974f569c0f226 /llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | |
| parent | 3cceffb752c7f5eb69c41226ddd9fb664683a204 (diff) | |
| download | bcm5719-llvm-eba9fdac7e131c6c99824cfd763989cc74965007.tar.gz bcm5719-llvm-eba9fdac7e131c6c99824cfd763989cc74965007.zip | |
[ARM] Correct handling of LSL #0 in an IT block
The check for LSL #0 in an IT block was checking if operand 4 was zero, but
operand 4 is the condition code operand so it was actually checking for LSLEQ.
Fix this by checking operand 3, which really is the immediate operand, and add
some tests.
Differential Revision: https://reviews.llvm.org/D30692
llvm-svn: 297142
Diffstat (limited to 'llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index de3b51ca5c7..f20ee1b91ac 100644 --- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -8940,7 +8940,7 @@ unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) { inITBlock()) return Match_RequiresNotITBlock; // LSL with zero immediate is not allowed in an IT block - if (Opc == ARM::tLSLri && Inst.getOperand(4).getImm() == 0 && inITBlock()) + if (Opc == ARM::tLSLri && Inst.getOperand(3).getImm() == 0 && inITBlock()) return Match_RequiresNotITBlock; } else if (isThumbOne()) { // Some high-register supporting Thumb1 encodings only allow both registers |
