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| author | Simon Tatham <simon.tatham@arm.com> | 2019-06-21 13:17:08 +0000 |
|---|---|---|
| committer | Simon Tatham <simon.tatham@arm.com> | 2019-06-21 13:17:08 +0000 |
| commit | bafb105e969755511a8281493b9f6f135a069c16 (patch) | |
| tree | 5bd38758d1ac274ff8065c40e4ce4a5a26cf0e0a /llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | |
| parent | 26cc5bcb1a392c9e352be35c50f18e1404d91159 (diff) | |
| download | bcm5719-llvm-bafb105e969755511a8281493b9f6f135a069c16.tar.gz bcm5719-llvm-bafb105e969755511a8281493b9f6f135a069c16.zip | |
[ARM] Add MVE vector instructions that take a scalar input.
This adds the `MVE_qDest_rSrc` superclass and all its instances, plus
a few other instructions that also take a scalar input register or two.
I've also belatedly added custom diagnostic messages to the operand
classes for odd- and even-numbered GPRs, which required matching
changes in two of the existing MVE assembly test files.
Reviewers: dmgreen, samparker, SjoerdMeijer, t.p.northover
Subscribers: javed.absar, kristof.beyls, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D62678
llvm-svn: 364040
Diffstat (limited to 'llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 17 |
1 files changed, 16 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index 4f76732fed0..eb16bece258 100644 --- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -1276,6 +1276,16 @@ public: RegShiftedImm.SrcReg); } bool isRotImm() const { return Kind == k_RotateImmediate; } + + template<unsigned Min, unsigned Max> + bool isPowerTwoInRange() const { + if (!isImm()) return false; + const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm()); + if (!CE) return false; + int64_t Value = CE->getValue(); + return Value > 0 && countPopulation((uint64_t)Value) == 1 && + Value >= Min && Value <= Max; + } bool isModImm() const { return Kind == k_ModifiedImmediate; } bool isModImmNot() const { @@ -5962,6 +5972,7 @@ StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic, !(hasMVE() && (Mnemonic == "vmine" || Mnemonic == "vshle" || Mnemonic == "vshlt" || Mnemonic == "vshllt" || + Mnemonic == "vrshle" || Mnemonic == "vrshlt" || Mnemonic == "vmvne" || Mnemonic == "vorne" || Mnemonic == "vnege" || Mnemonic == "vnegt" || Mnemonic == "vmule" || Mnemonic == "vmult" || @@ -5987,7 +5998,8 @@ StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic, Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" || Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" || Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" || - Mnemonic == "bxns" || Mnemonic == "blxns" || + Mnemonic == "bxns" || Mnemonic == "blxns" || Mnemonic == "vfmas" || + Mnemonic == "vmlas" || (Mnemonic == "movs" && isThumb()))) { Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1); CarrySetting = true; @@ -6345,6 +6357,9 @@ bool ARMAsmParser::shouldOmitVectorPredicateOperand(StringRef Mnemonic, if (!hasMVE() || Operands.size() < 3) return true; + if (Mnemonic.startswith("vctp")) + return false; + if (Mnemonic.startswith("vmov") && !(Mnemonic.startswith("vmovl") || Mnemonic.startswith("vmovn") || Mnemonic.startswith("vmovx"))) { |

